MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 81

• Manufacturer Part Number: MT46H8M32LFB5-6IT:H
• Description: MICMT46H8M32LFB5-6_IT:H MDDDR
• Manufacturer: Micron Technology Inc

PRECHARGE Operation
Auto Precharge
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256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access
some specified time (
mines whether one or all banks will be precharged, and in the case where only one bank
is precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all banks are pre-
charged (A10 = HIGH), inputs BA0 and BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state), or if the previously open row is
already in the process of precharging.
Auto precharge is a feature that performs the same individual bank PRECHARGE func-
tion described previously, without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent; it is either enabled or disabled for each individual
READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This earliest valid stage is determined as if an explicit PRECHARGE command
was issued at the earliest possible time without violating
each burst type in Table 16 (page 42). The READ with auto precharge enabled state or
the WRITE with auto precharge enabled state can each be broken into two parts: the ac-
cess period and the precharge period. The access period starts with registration of the
command and ends where
charge, the precharge period is defined as if the same burst was executed with auto pre-
charge disabled, followed by the earliest possible PRECHARGE command that still ac-
cesses all the data in the burst. For WRITE with auto precharge, the precharge period
begins when
tion, during a WRITE with auto precharge, at least one clock is required during
time. During the precharge period, the user must not issue another command to the
same bank until
This device supports
single WRITE with auto precharge issued at
delayed until
Bank READ operations with and without auto precharge are shown in Figure 44
(page 83) and Figure 45 (page 84). Bank WRITE operations with and without auto
precharge are shown in Figure 46 (page 85) and Figure 47 (page 86).
t
t
WR ends, with
RAS (MIN) has been satisfied.
t
RP is satisfied.
t
t
RAS lock-out. In the case of a single READ with auto precharge or
RP) after the PRECHARGE command is issued. Input A10 deter-
t
RP (the precharge period) begins. For READ with auto pre-
t
WR measured as if auto precharge was disabled. In addi-
81
256Mb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RCD (MIN), the internal precharge will be
t
PRECHARGE Operation
RAS (MIN), as described for
© 2008 Micron Technology, Inc. All rights reserved.
t
WR