MT46H8M32LFB5-6IT:H Micron Technology Inc, MT46H8M32LFB5-6IT:H Datasheet - Page 80
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MT46H8M32LFB5-6IT:H
Manufacturer Part Number
MT46H8M32LFB5-6IT:H
Description
MICMT46H8M32LFB5-6_IT:H MDDDR
Manufacturer
Micron Technology Inc
Datasheet
1.MT46H8M32LFB5-6ITH.pdf
(96 pages)
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Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. I 09/10 EN
Command
Address
DQS
DQS
DQS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DM
DM
DM
DQ
DQ
DQ
CK#
5, 6
5, 6
5, 6
CK
1
7
6
7
6
7
6
WRITE
Bank a,
Col b
T0
Notes:
2
t
t
t
DQSS
DQSS
DQSS
1. An interrupted burst of 8 is shown; one data element is written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4.
5. DQS is required at T4 and T4n to register DM.
6. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. D
D
b
IN
t
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
D
IN
T1
b
IN
b = data-in for column b.
D
b
IN
T1n
NOP
T2
T2n
80
T3
NOP
256Mb: x16, x32 Mobile LPDDR SDRAM
t
WR
T3n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
4
NOP
T4
Don’t Care
T4n
(a or all)
T5
PRE
Bank
© 2008 Micron Technology, Inc. All rights reserved.
3
WRITE Operation
Transitioning Data
T6
NOP
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