LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 96

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

Revision 1.0 (03-17-05)
13-12
BITS
11-3
2
1
0
DESCRIPTION
Threshold Control Bits (TR). These control the transmit threshold values
the MIL should use. These bits are used when the SF bit is reset. The host
can program the Transmit threshold by setting these bits. The intent is to
allow the MIL to transfer data to the final destination only after the threshold
value is met.
In 10Mbps mode (TTM = 1) the threshold is set as follows:
In 100Mbps mode (TTM = 0) the threshold is set by as follows:
Reserved
32/16-bit Mode. When set, the LAN9118 is set for 32-bit operation. When
clear, it is configured for 16-bit operation. This field is the value of the
D32/nD16 strap.
Soft Reset Time-out (SRST_TO).
internal PHY is not in the operational state (RX_CLK and TX_CLK running), the reset
will not complete and the soft reset operation will time-out and this bit will be set to a
‘1’. The host processor must correct the problem and issue another soft reset.
Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset
generates a full reset of the PHY Registers and MAC CSR’s. The SCSR’s
(system command and status registers) are reset except for any NASR bits.
Soft reset also clears any TX or RX errors (TXE/RXE). This bit is self-
clearing.
Note:
Note:
Do not attempt a soft reset unless the internal PHY is fully awake
and operational. After a PHY reset, or when returning from a
reduced power state, the PHY must given adequate time to return
to the operational state before a soft reset can be issued. The
internal RX_CLK and TX_CLK signals must be running for a proper
software reset. Please refer to
page 162
The LAN9118 must always be read at least once after power-up,
reset, or upon return from a power-saving state or write operations
will not function.
[13]
[13]
0
0
1
1
0
0
1
1
for details on PHY reset timing.
[12]
[12]
0
1
0
1
0
1
0
1
If a software reset is attempted when the
DATASHEET
Section 7.8, "Reset Timing," on
Threshold (DWORDS)
Threshold (DWORDS)
96
High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
020h
040h
080h
100h
012h
018h
020h
028h
TYPE
R/W
RO
RO
RO
SC
SMSC LAN9118
DEFAULT
Datasheet
00
0
0
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