LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 157

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
7.5
SYMBOL
t
t
t
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
ah
In this mode the upper address inputs are not decoded, and any burst read of the LAN9118 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9118. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or
WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS)
or Read Enable (nRD). When either or both of these control signals go high, they must remain high
for the period specified.
Timing for 16-bit and 32-bit RX Data FIFO Direct PIO Burst Reads is identical with the exception that
D[31:16] are not driven during a 16-bit burst. Note that address lines A[2:1] are still used, and address
bits A[7:3] are ignored.
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
RX Data FIFO Direct PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Figure 7.4 RX Data FIFO Direct PIO Burst Read Cycle Timing
Table 7.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
DATASHEET
157
MIN
13
45
0
0
0
TYP
Revision 1.0 (03-17-05)
MAX
30
40
7
UNITS
ns
ns
ns
ns
ns
ns