LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 111

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
6.3.20
BITS
29-8
7-0
31
30
DESCRIPTION
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
R/nW. When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
Reserved.
CSR Address. The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
MAC_CSR_CMD – MAC CSR Synchronizer Command Register
This register is used to control the read and write operations with the MAC CSR’s
Offset:
A4h
DATASHEET
111
Size:
32 bits
TYPE
R/W
R/W
SC
RO
Revision 1.0 (03-17-05)
DEFAULT
00h
0
0
-