LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 51

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately. If
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately,
SMSC LAN9118
4.11.3
4.11.4
4.11.5
4.11.5.1
4.11.5.2
After the “READY” bit is set, the LAN9118 can be configured via its control registers. The nRESET
signal is pulled-high internally by the LAN9118 and can be left unconnected if unused. If used, nRESET
must be driven low for a minimum period as defined in
Resume Reset Timing
After issuing a write to the BYTE_TEST register to wake the LAN9118 from a power-down state, the
READY bit in PMT_CTRL will assert (set High) within 2ms.
Soft Reset (SRST)
Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will
return to ‘0’ after approximately 2 µs, at which time the Soft Reset is complete. Soft reset does not
clear control register bits marked as NASR.
PHY Reset Timing
The following sections and tables specify the operation and time required for the internal PHY to
become operational after various resets or when returning from the reduced power state.
PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This
self-clearing bit will return to ‘0’ after approximately 100 µs, at which time the PHY reset is complete.
PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register.
This self-clearing bit will return to ‘0’ at which time the PHY reset is complete.
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
(within 2µs). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
DATASHEET
51
Section 7.8, "Reset Timing," on page
Revision 1.0 (03-17-05)
162.