LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 163

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
7.9
SYMBOL
t
t
t
t
t
CSHCKH
t
t
t
t
t
CKLCSL
CKHDIS
CKCYC
DVCKH
DSCKH
DHCKH
CKLDIS
CSHDV
DHCSL
t
t
t
CKH
CKL
CSL
The following specifies the EEPROM timing requirements for the LAN9118
EEPROM Timing
EECLK Cycle time
EECLK High time
EECLK Low time
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDIO valid before rising edge of EECLK
(OUTPUT)
EEDIO disable after rising edge EECLK
(OUTPUT)
EEDIO setup to rising edge of EECLK
(INPUT)
EEDIO hold after rising edge of EECLK
(INPUT)
EECLK low to data disable (OUTPUT)
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
DESCRIPTION
Table 7.10 EEPROM Timing Values
Figure 7.7 EEPROM Timing
DATASHEET
163
1070
1070
1110
MIN
550
550
550
580
550
30
90
0
0
TYP
Revision 1.0 (03-17-05)
MAX
1130
570
570
600
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns