LAN9118MT Standard Microsystems (SMSC), LAN9118MT Datasheet - Page 45

• Manufacturer Part Number: LAN9118MT
• Manufacturer: Standard Microsystems (SMSC)

High-Performance Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
SMSC LAN9118
4.9.2.2
4.9.2.3
4.9.2.4
EEDIO (OUTPUT)
EEDIO (INPUT)
EECLK
EECS
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
Table 4.8, "Required EECLK
each EEPROM operation.
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates
a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC
address.
EEPROM Command and Data Registers
Refer to
"E2P_DATA – EEPROM Data Register," on page 118
Supported EEPROM operations are described in these sections.
EEPROM Timing
Refer to
Section 6.3.23, "E2P_CMD – EEPROM Command Register," on page 115
Section 7.9, "EEPROM Timing," on page 163
1
0
0
Figure 4.10 EEPROM WRAL Cycle
Table 4.8 Required EECLK Cycles
OPERATION
ERASE
WRITE
EWDS
EWEN
0
WRAL
READ
ERAL
Cycles", shown below, shows the number of EECLK cycles required for
1
DATASHEET
45
REQUIRED EECLK CYCLES
D7
for detailed EEPROM timing specifications.
for a detailed description of these registers.
10
10
10
10
18
18
18
D0
t
CSL
Revision 1.0 (03-17-05)
and
Section 6.3.24,