LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 6 of 397
- Download datasheet (10Mb)
Lattice Semiconductor
LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide
Power Estimation and Management for LatticeECP/EC and LatticeXP Devices
Introduction ...................................................................................................................................................... 11-1
Features ........................................................................................................................................................... 11-1
Functional Description...................................................................................................................................... 11-1
LatticeECP/EC and LatticeXP PLL Primitive Definitions.................................................................................. 11-4
PLL Usage in IPexpress................................................................................................................................... 11-7
Equations for Generating Input and Output Frequency Ranges .................................................................... 11-10
Clock Distribution in LatticeECP/EC and LatticeXP ....................................................................................... 11-11
Clock Net Preferences ................................................................................................................................... 11-12
Dynamic Clock Selection (DCS) .................................................................................................................... 11-14
Other Design Considerations ......................................................................................................................... 11-17
DCS Usage with VHDL .................................................................................................................................. 11-18
Technical Support Assistance........................................................................................................................ 11-19
Revision History ............................................................................................................................................. 11-19
Appendix A. Clock Preferences ..................................................................................................................... 11-20
Introduction ...................................................................................................................................................... 12-1
Power Supply Sequencing and Hot Socketing................................................................................................. 12-1
Power Calculator Hardware Assumptions........................................................................................................ 12-1
Power Calculator.............................................................................................................................................. 12-1
PLL Divider and Delay Blocks................................................................................................................. 11-1
PLL Inputs and Outputs .......................................................................................................................... 11-2
PLL Attributes.......................................................................................................................................... 11-3
PLL Attributes Definitions........................................................................................................................ 11-4
Dynamic Delay Adjustment ..................................................................................................................... 11-6
Including sysCLOCK PLLs in a Design................................................................................................... 11-7
IPexpress Usage..................................................................................................................................... 11-7
EHXPLLB Example Projects ................................................................................................................... 11-9
f
f
Primary Clock Sources and Distribution................................................................................................ 11-11
Primary-Pure and Primary-DCS............................................................................................................ 11-12
Global Primary Clock and Quadrant Primary Clock .............................................................................. 11-12
Secondary Clock Sources and Distribution........................................................................................... 11-13
Limitations on Secondary Clock Availability.......................................................................................... 11-13
DCS Waveforms ................................................................................................................................... 11-15
Use of DCS with PLL ............................................................................................................................ 11-17
Jitter Considerations ............................................................................................................................. 11-17
Simulation Limitations ........................................................................................................................... 11-17
PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available ................. 11-18
DCS Usage with Verilog........................................................................................................................ 11-18
ASIC...................................................................................................................................................... 11-20
FREQUENCY........................................................................................................................................ 11-20
MAXSKEW............................................................................................................................................ 11-20
MULTICYCLE ....................................................................................................................................... 11-20
PERIOD ................................................................................................................................................ 11-20
PROHIBIT ............................................................................................................................................. 11-20
CLOCK_TO_OUT ................................................................................................................................. 11-20
INPUT_SETUP ..................................................................................................................................... 11-21
PLL_PHASE_BACK.............................................................................................................................. 11-21
Power Calculator Equations.................................................................................................................... 12-2
Starting the Power Calculator ................................................................................................................. 12-3
Starting a Power Calculator Project ........................................................................................................ 12-5
Power Calculator Main Window .............................................................................................................. 12-6
VCO
PFD
Constraint ...................................................................................................................................... 11-10
Constraint ..................................................................................................................................... 11-10
5
LatticeXP Family Handbook
Table of Contents
Related parts for LFXP6C-4QN208I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LFXP6C-4TN144I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
Datasheet:
![LFXP6C-4QN208C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP6C-4FN256C](/photos/16/14/161486/bga256_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 188 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
![LFXP6C-4T144I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
![LFXP6C-4T144C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
![LFXP6C-4Q208C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
![LFXP6C-4Q208I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
![LFXP6C-3F256I](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
IC FPGA 5.8KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
![LFXP6C-3QN208C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 142 I/O
Manufacturer:
Lattice
Datasheet:
![LFXP6C-5TN144C](/images/manufacturer_photos/0/3/380/lattice_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 100 I/O
Manufacturer:
Lattice
Datasheet:
![LFXP6C-5QN208C](/photos/19/4/190400/ge208pqfp05-40_tmb.jpg)
Part Number:
Description:
FPGA, 1.8V FLASH, INSTANT ON, SMD
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP6C-4F256I](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
![LFXP6C-5F256C](/images/manufacturer_photos/0/3/381/lattice_semiconductor_tmb.jpg)
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 400MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet: