LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 238
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LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Appendix A. Using IPexpress™ to Generate DDR Modules
The input and output DDR module can be generated using IPexpress. The I/O section under the Architecture mod-
ules provides two options to the user:
IPexpress generates only the modules that are implemented within the IOLOGIC. Any logic required in the FPGA
core to complete the memory interface must be implemented by the user.
Figure 10-18. IPexpress I/O Section
DDR Generic
DDR Generic will generate the output DDR (ODDRXB) primitives for a given bus width. The user has the option to
enable or disable tristate control to the output DDR registers. Figure 10-19 shows the DDR Generic views of IPex-
press.
1. DDR_GENERIC – The option allows generation of a Generic DDR interface, which in the case of Lat-
2. DDR_MEM – This option allows the user to generate a complete DDR memory interface. It will generate
ticeECP/EC and LatticeXP devices, is only the output side DDR. The input side for a Generic DDR inter-
face must be implemented using PFU registers. Appendix D provides the example code for the input side
generic DDR.
both the read and write side interface required to interface with the memory.
10-19
LatticeECP/EC and LatticeXP
DDR Usage Guide
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