LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 274

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
PCB Layout Recommendations for VCCPLL and GNDPLL if Separate Pins are Available
It is best to connect VCCPLL to VCC at a single point using a filter and to create a separate GNDPLL plane directly
under it (tied via a single point to GND).
Separate islands for both VCCPLL and GNDPLL are recommended if applicable.
DCS Usage with Verilog
module dcs(clk0,clk1,sel,dcsout);
input clk0, clk1, sel;
output dcsout;
DCS DCSInst0 (.SEL(sel),.CLK0(clk0),.CLK1(clk1),.DCSOUT(dcsout));
defparam DCSInst0.DCSMODE = "CLK0";
endmodule
DCS Usage with VHDL
COMPONENT DCS
-- synthesis translate_off
-- synthesis translate_on
END COMPONENT;
begin
DCSInst0: DCS
-- synthesis translate_off
-- synthesis translate_on
);
attribute DCSMODE : string;
attribute DCSMODE of DCSinst0 : label is "POS";
GENERIC
PORT
GENERIC MAP(
PORT MAP
(
DCSMODE : string :=
);
(
CLK0
CLK1
SEL
DCSOUT
);
DCSMODE
)
(
SEL
CLK0
CLK1
DCSOUT
=> "POS"
:IN
:IN
:IN
:OUT
=>
=>
=>
=>
clksel,
dcsclk0,
sysclk1,
dcsclk
std_logic;
std_logic;
std_logic;
std_logic
"POS"
11-18
sysCLOCK PLL Design and Usage Guide
LatticeECP/EC and LatticeXP