LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 265

• Manufacturer Part Number: LFXP6C-4QN208I
• Description: FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: Lattice

Specifications of LFXP6C-4QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 6000
• Maximum Internal Frequency: 360 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 142
• Ram Bits: 73728
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
Figure 11-7. Configuration Tab
Divider Mode: In this mode, the user sets the input frequency and divider settings. It is assumed the user is famil-
iar with the PLL operation. The user must choose the CLKOP Divider value to maximize the f
to achieve opti-
VCO
mum PLL performance. After input frequency and divider settings are set, clicking the ‘Calculate’ button will display
the output frequencies. If the divider settings are out of the PLL specification, the software will generate an error.
EHXPLLB Example Projects
ispLEVER provides example PLL projects for first time PLL users.
In the ispLEVER Project Navigator, go to the File menu and select Open Examples....
Select the FPGA folder. The LatticeEC and LatticeXP folders include PLL example projects in both Verilog and
VHDL.
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