LFXP6C-4QN208I Lattice, LFXP6C-4QN208I Datasheet - Page 300
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LFXP6C-4QN208I
Manufacturer Part Number
LFXP6C-4QN208I
Description
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer
Lattice
Specifications of LFXP6C-4QN208I
Package
208PQFP
Family Name
LatticeXP
Device Logic Units
6000
Maximum Internal Frequency
360 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
142
Ram Bits
73728
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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LatticeXP sysCONFIG
Usage Guide
September 2008
Technical Note TN1082
Introduction
The memory in the LatticeXP™ FPGAs is built using Flash cells, along with SRAM cells, so that configuration
memory can be loaded automatically at power-up, or at any time the user wishes to update the device. In addition
to “instant-on” capability, on-chip Flash memory greatly increases design security by getting rid of the external con-
figuration bitstream; while maintaining the ease of use and reprogrammability of an SRAM-based FPGA.
While an external device is not required, the LatticeXP does support several external configuration modes. The
available external configuration modes are:
• Slave Serial
• Master Serial
• Slave Parallel
• ispJTAG™ (1149.1 interface)
This guide will cover all the configuration options available for the LatticeXP.
Programming Overview
The LatticeXP contains two types of memory, SRAM and Flash (refer to Figure 13-1). SRAM contains the FPGA
configuration, essentially the “fuses” that define the circuit connections; Flash provides an internal storage space
for the configuration data.
The SRAM can be configured using JTAG, one of the external configuration modes, or by using the data stored in
on-chip Flash. The configuration process consists of SRAM initialization (clear the RAM and the address pointers),
loading the SRAM with the configuration data, and setting the FPGA into user mode (waking up the FPGA).
On-chip Flash can be programmed by using JTAG or by using the external Slave Parallel port. JTAG Flash pro-
gramming can be performed any time the device is powered up. The Slave Parallel port uses the sysCONFIG™
pins and can program the Flash directly or in the background. Direct programming takes place during config mode,
background programming during user mode. The FPGA enters config mode at power up, when the PROGRAMN
pin is pulled low, or when a refresh command is issued via JTAG; it enters user mode when it wakes up, i.e. when
the device begins running user code. These two programming modes, direct and background, will be referred to in
this document as Flash Direct and Flash Background.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
13-1
tn1082_01.9
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