EVAL-AD9388AFEZ_3 Analog Devices Inc, EVAL-AD9388AFEZ_3 Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD9388AFEZ_3
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9388AFEZ_3

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Pin No.
2
3
4
5
6
7
8
9
10
48
124
1
G = ground, P = power, I = input, and O = output.
Mnemonic
SPDIF
I2S0
I2S1
I2S2
I2S3
LRCLK
SCLK
MCLKOUT
EXT_CLAMP
EXT_CLK
RTERM
Type
O
O
O
O
O
O
O
O
I
I
I
1
Rev. D | Page 15 of 24
Description
SPDIF Digital Audio Output.
I
I
I
I
Data Output Clock for Left and Right Audio Channels.
Audio Serial Clock Output.
Audio Master Clock Output.
External Clamp Signal. This is an optional mode of operation for the AD9388A.
Clock Input for External Clock and Clamp Mode. This is an optional mode of
operation for the AD9388A.
Sets Internal Termination Resistance. Connect this pin to TGND using a 500 Ω
resistor.
2
2
2
2
S Audio for Channel 1 and Channel 2.
S Audio for Channel 3 and Channel 4.
S Audio for Channel 5 and Channel 6.
S Audio for Channel 7 and Channel 8.
AD9388A