EVAL-AD9388AFEZ_3 Analog Devices Inc, EVAL-AD9388AFEZ_3 Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD9388AFEZ_3
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD9388AFEZ_3

• Lead Free Status / Rohs Status: Supplier Unconfirmed

AD9388A
Pin No.
24 to 33, 36 to 47,
52 to 55, 58 to 61
19
20
17
18
16
11
12
13
21
51
65
66
70
102
85
86
90
92
63
62
75
97
112
113
115
116
118
119
121
122
106
1
105
144
Mnemonic
P0 to P29
INT1
SYNC_OUT/INT2
HS/CS
VS/FIELD
DE/FIELD
SDA
SCL
ALSB
RESET
LLC
XTAL1
XTAL
ELPF
AUDIO_ELPF
REFOUT
CML
REFN
REFP
HS_IN/CS_IN
VS_IN
SOG
SOY
RXA_CN
RXA_CP
RXA_0N
RXA_0P
RXA_1N
RXA_1P
RXA_2N
RXA_2P
DDCA_SDA
TEST6
DDCA_SCL
TEST7
Type
O
O
O
O
O
O
I/O
I
I
I
O
O
I
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I
I
1
Rev. D | Page 14 of 24
Test Pin. Connect this pin to DGND using a 10 kΩ resistor.
Description
Video Pixel Output Port.
Interrupt. Can be active low or active high. The set of events that triggers an
interrupt is under user control.
Sliced Synchronization Output Signal (SYNC_OUT).
Interrupt Signal (INT2).
Horizontal Synchronization Output Signal (HS).
Composite Synchronization (CS). A single signal containing both horizontal
and vertical synchronization pulses.
Vertical Synchronization Output Signal (VS).
Field Synchronization (FIELD). Field synchronization output signal in all
interlaced video modes.
Data Enable Signal (DE). Indicates active pixel data.
Field Synchronization (FIELD). Field synchronization output signal in all
interlaced video modes.
I
I
line for the control port.
This pin sets the second LSB of each AD9388A register map.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is
required to reset the AD9388A circuitry.
Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz.
This pin should be connected to the 28.63636 MHz crystal or left as a no connect
if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the
AD9388A. In crystal mode, the crystal must be a fundamental crystal.
Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an
external 3.3 V, 28.63636 MHz clock oscillator source to clock the AD9388A.
The recommended external loop filter must be connected to this ELPF pin.
The recommended external loop filter must be connected to AUDIO_ELPF.
Internal Voltage Reference Output.
Common-Mode Level for the Internal ADCs.
Internal Voltage Output.
Internal Voltage Output.
HS Input Signal. Used in analog mode for 5-wire timing mode.
CS Input Signal. Used in analog mode for 4-wire timing mode.
For optimal performance, a 100 Ω series resistor is recommended on the
HS_IN/CS_IN pin.
VS Input Signal. This pin is used in analog mode for 5-wire timing mode. For
optimal performance, a 100 Ω series resistor is recommended on the VS_IN pin.
Synchronization-on-Green Input. This pin is used in embedded
synchronization mode.
Synchronization-on-Luma Input. This pin is used in embedded
synchronization mode.
Digital Input Clock Complement of Port A in the HDMI Interface.
Digital Input Clock True of Port A in the HDMI Interface.
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
Digital Input Channel 0 True of Port A in the HDMI Interface.
Digital Input Channel 1 Complement of Port A in the HDMI Interface.
Digital Input Channel 1 True of Port A in the HDMI Interface.
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
Digital Input Channel 2 True of Port A in the HDMI Interface.
HDCP Slave Serial Data Port A.
Test Pin. Do not connect.
HDCP Slave Serial Clock Port A.
2
2
C Port Serial Data Input/Output. SDA is the data line for the control port.
C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock