MT47H32M16HR-3:FTR Micron Technology Inc, MT47H32M16HR-3:FTR Datasheet - Page 15
![](/photos/31/34/313419/mfg557-84-fbga_sml.jpg)
MT47H32M16HR-3:FTR
Manufacturer Part Number
MT47H32M16HR-3:FTR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16HR-3FTR.pdf
(131 pages)
Specifications of MT47H32M16HR-3:FTR
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
250mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT47H32M16HR-3:FTR
Manufacturer:
MICRON/镁光
Quantity:
20 000
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
RAS#, CAS#, WE#
LDM, UDM, DM
A[13:0] (x4, x8)
DQ[15:0] (x16)
A[12:0] (x16)
DQ[3:0] (x4)
DQ[7:0] (x8)
BA0, BA1
Symbol
CK, CK#
ODT
CKE
CS#
Type
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
Bank address inputs: BA[1:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[2:0] define which mode register including MR,
EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE power-
down (row active in any bank). CKE is synchronous for power-down entry, power-down
exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH
exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an
SSTL_18 input but will detect a LVCMOS LOW level once V
up. After V
must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH
operation, V
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered high. CS# provides for exter-
nal bank selection on systems with multiple ranks. CS# is considered part of the com-
mand code.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on
both edges of DQS. Although DM balls are input-only, the DM loading is designed to
match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for
upper byte DQ[15:8].
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,
RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input
will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
Data input/output: Bidirectional data bus for 32 Meg x 16.
Bidirectional data bus for 128 Meg x 4.
Bidirectional data bus for 64 Meg x 8.
REF
REF
has become stable during the power-on and initialization sequence, it
must be maintained.
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
512Mb: x4, x8, x16 DDR2 SDRAM
DD
is applied during first power-
© 2004 Micron Technology, Inc. All rights reserved.