MT47H32M16HR-3:FTR Micron Technology Inc, MT47H32M16HR-3:FTR Datasheet - Page 100
![](/photos/31/34/313419/mfg557-84-fbga_sml.jpg)
MT47H32M16HR-3:FTR
Manufacturer Part Number
MT47H32M16HR-3:FTR
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16HR-3FTR.pdf
(131 pages)
Specifications of MT47H32M16HR-3:FTR
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
250mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT47H32M16HR-3:FTR
Manufacturer:
MICRON/镁光
Quantity:
20 000
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Figure 54: x16 Data Output Timing –
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. Q 10/10 EN
DQ8–DQ15 and UDQS collectively 6
DQ0–DQ7 and LDQS collectively 6
DQ (first data no longer valid) 4
DQ (first data no longer valid) 4
DQ (first data no longer valid) 7
DQ (first data no longer valid) 7
DQ (last data valid) 4
DQ (last data valid) 4
DQ (last data valid) 7
DQ (last data valid) 7
Notes:
UDQS#
UDQS 3
LDSQ#
LDQS 3
1.
2.
3. DQ transitioning after the DQS transitions define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
CK#
CK
t
t
transitions, and ends with the last valid transition of DQ.
lower byte, and UDQS defines the upper byte.
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
T1
t HP 1
t
DQSQ,
t HP 1
t
CL or
t DQSQ 2
t
t QH 5
QH, and Data Valid Window
t DQSQ 2
T2
t QH 5
Data valid
t
window
100
CH clock transitions collectively when a bank is active.
Data valid
T2
T2
T2
t HP 1
window
T2
T2
T2
t DQSQ 2
t QHS
T2n
t QH 5
t DQSQ 2
t QHS
t QH 5
Data valid
window
t HP 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2n
T2n
T2n
Data valid
window
T2n
T2n
T2n
512Mb: x4, x8, x16 DDR2 SDRAM
T3
t DQSQ 2
t QHS
t QH 5
t QHS
t DQSQ 2
t QH 5
t HP 1
Data valid
window
Data valid
window
T3
T3
T3
T3
T3n
T3
T3
t
DQSQ window. LDQS defines the
t DQSQ 2
t DQSQ 2
t QHS
t QHS
t HP 1
t QH 5
t QH 5
Data valid
window
Data valid
© 2004 Micron Technology, Inc. All rights reserved.
window
T3n
T4
T3n
T3n
T3n
T3n
T3n
t QHS
t QHS
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