STV3550B STMicroelectronics, STV3550B Datasheet - Page 79

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
Figure 50. Typical refresh access cycle
6.3.10
6.3.11
NOT_CS_SDRAM
CKOUT_SDRAM
RD_NOT_WR
SDRAM low power mode
Memory configurations
The STV3550 is able to set the SDRAM into low power mode. Most SDRAM devices have a
clock enable input pin that internally gates the SDRAM clock supplied by the STV3550.
The STV3550 does not have the corresponding output pin included in its memory interface,
but this feature can be emulated using any of the standard STV3550 I/Os.
However, the STV3550 memory interface provides control over the SDRAM clock in order to
switch the I/O without any timing violations according to low power mode entry and exit
specified for the SDRAM devices.
In all the following configurations, the Flash device has always 16 data lines and no more
than 20 address lines.
The Flash device does not receive any clock signals from the STV3550, and the STV3550
considers the Flash memory as an asynchronous device.
The SDRAM device always receives clock signals from the STV3550.
The address bus is always shared between the SDRAM and Flash memories. Additional
memory parameters can be adjusted through software (SDRAM size and organization,
Flash latency, etc.).
Low-cost configuration
This configuration requires a SDRAM device with 16 data lines. A typical SDRAM size may
be 64 Mbits (8 MBytes).
The Flash data bus is separate from the SDRAM data bus. Therefore, constraints when
placing the devices are reduced, i.e. wires are short and wire loads are small.
Since 16-bit data words are used, address outputs ADDR[11:0] are connected to the
SDRAM address bus and address outputs ADDR[16:15] are used as Bank Activate signals.
Flash is a read-only device.
NOT_CAS
NOT_RAS
CPU and system management functional description
1 cycle
RefreshTime
PrechargeTime
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