STV3550B STMicroelectronics, STV3550B Datasheet - Page 113

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

STV3550
7.7.19
START/STOP condition detection
Figure 73. Clock synchronisation mechanism
The SSC2 implements this clock synchronization mechanism when the I²C control bit,
SSCI2CM, is enabled.
START/STOP conditions are only generated by a master device. A slave device must detect
the START condition and expect the next byte (or 2 bytes in 10-bit addressing) to be a slave
address. A STOP condition is used to detect when the bus is free.
A START condition is when the transmit/receive data line goes from high to low DURING the
high period of the clock line. It indicates that a master device wants control of the bus. In a
single master configuration, it will automatically get control, in a multi-master configuration, it
begins to transmit as part of the arbitration procedure, and may or may not get control.
A STOP condition is when the transmit/receive data line goes from low to high DURING the
high period of the clock line. It indicates that a master device has relinquished control of the
bus (the bus will be free a specified time after the stop condition).
An additional piece of hardware is provided on the SSC2 to detect START and STOP
conditions. This is necessary in slave mode because it cannot be done in time by
programming the PIO pads. There is not sufficient time for a software interrupt between the
end of the START condition and the beginning of the data transmitted by a remote master.
START and STOP conditions are detected by sampling the data line continuously when the
clock line is high. The same edge detection mechanism as for the serial clock is used to
determine if the data line changes. If a falling edge is seen then a START condition is
detected. If a rising edge is seen then a STOP condition is detected. The sampling approach
allows an element of spike suppression on the data line.
The START and STOP condition detection is enabled when the I²C control bit, SSCI2CM, is
set in the I²C control register.
When a START condition is triggered, the SSC2 will inform the I²C control block which will
then initiate the address comparison phase.
When a STOP condition is triggered the SSC2 will set the SSCSTOP bit in the status
register. It will also generate an interrupt if the SSCSTOPEN bit is set in the interrupt enable
register.
The interrupt and the status bit will be cleared when the status register is read.
Master 1
Master 2
Resultant
Clock
Stretched
Slave
High Period
Master 2
Master 1 Low
Period
Slave
Stretch
TV chassis control
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