STV3550B STMicroelectronics, STV3550B Datasheet - Page 74

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

CPU and system management functional description
6.3.8
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STV3550 memory interface capabilities regarding Flash device
Supported Flash commands
The STV3550 is able to read the Flash memory like an asynchronous memory device.
Write operations in Flash require specific sequences on the data and address buses. Since
the STV3550 can drive any data and any addresses on the buses, write operations into
Flash can be performed if the Flash device is used as an asynchronous memory.
Control signals such as chip select, write enable and output enable (active low) can be
configured by software, so that they are asserted or not by the STV3550 memory interface
during each operation.
Flash requirements
Time is expressed in number of STV3550 system clock cycles. Phase refers to half a cycle.
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Flash size up to 16 Mbits
Access cycle time from 2 to 127 cycles (t
Bus release time from 0 to 15 cycles (t
Data drive delay from 0 to 31 phases after start of access cycle (t
Falling edge of NOT_CS_FLASH from 0 to 15 phases or cycles after start of Read
Access Cycle (t
Rising edge of NOT_CS_FLASH from 0 to 15 phases or cycles before end of Read
Access Cycle (t
Falling edge of NOT_CS_FLASH from 0 to 15 phases or cycles after start of Write
Access Cycle (t
Rising edge of NOT_CS_FLASH from 0 to 15 phases or cycles before end of Write
Access Cycle (t
Falling edge of NOT_CAS (NOT_OE) from 0 to 15 phases or cycles after start of Read
Access Cycle (t
Rising edge of NOT_CAS (NOT_OE) from 0 to 15 phases or cycles before end of Read
Access Cycle (t
Falling edge of RD_NOT_WR from 0 to 15 phases or cycles after start of Write Access
Cycle (t
Rising edge of RD_NOT_WR from 0 to 15 phases or cycles before end of Write Access
Cycle (t
Latch Point from 0 to 15 cycles before end of Access Cycle (t
WE1
WE2
)
)
CSr1
CSr2
CSw1
CSw2
OE1
OE2
)
)
)
)
)
)
BR
AC
)
)
LP
)
DD
)
STV3550