STV3550B STMicroelectronics, STV3550B Datasheet - Page 102

• Manufacturer Part Number: STV3550B
• Manufacturer: STMicroelectronics

Specifications of STV3550B

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

TV chassis control
7.7.5
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Clock control
In master mode, the serial clock, SCL, is generated by the SSC2 according to the setting of
the phase, SSCPH, and polarity, SSCPO bits in the control register.
The polarity bit, SSCPO, defines the logic level the clock idles at i.e. when the SSC2 is in
master mode, but is between transactions. A polarity bit of 1 indicates an idle level of logic 1,
0 indicates idle of logic 0.
The phase bit, SSCPH, indicates whether a pulse is generated in the first or second half of
the cycle. Note that this is a pulse relative to the idle state of the clock line i.e. if polarity is 0
then the pulse is positive going, if polarity is 1 then the pulse will be negative going. A phase
setting of 0 causes the pulse to be in the second half of the cycle, a setting of 1 causes the
pulse to occur in the first half of the cycle. The different combinations of polarity and phase
are shown in
Figure 67. Clock polarity and phase control
The SSC2 will always latch incoming data in the middle of the clock period at the point
shown in the diagram. With the different combinations of polarity and phase it is possible to
generate or not generate a clock pulse before the first data bit is latched.
Shifting out of data occurs at the end of the clock period. At the start of the first clock period
the shift register is loaded. At the end of the last clock period, the shift register is unloaded
into the receive buffer.
Baud rate generation
The SSC2 can generate a range of different baud rate clocks in master mode. These are
setup by programming the baud rate generator register, SSCBRG.
Writing this register programs the baud rate as defined by the following formulas.
SSCPO SSCPH
0
0
1
1
SDA Pin
Figure
0
1
0
1
Load
67.
Latch Shift Latch Shift Latch Unload
Load
Latch Shift Latch Shift Latch Unload
STV3550