MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 74

• Manufacturer Part Number: MCC501RX200TD0B
• Manufacturer: Freescale Semiconductor

Specifications of MCC501RX200TD0B

• Package Type: BGA
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

74
Table 39 System Clock Timing Description
*
†
C5NP
SYMBOL
Tsc
Tsh
Tsl
Tcc0
Tcc1
Tcc2
Tcc3
Tcc4
Tcc5
Tcc6
Tcc7
Tcch
Tccl
Pulse duty cycle measured at crossing voltage of SCLK/SCLKX
The frequencies specified for CCLK0 - CCLK7 allow full flexibility for the C-5 NP . Clock inputs associated with a specific protocol should be tied to ground
when that protocol is not used by the C-5 NP . It is also possible to use one or more CCLKn inputs for other frequencies; contact your C-Port
representative for more information.
CP Timing Specifications
CHAPTER 3: ELECTRICAL SPECIFICATIONS
PARAMETER
System Cycle Time 6.0
Sys Clk High Pulse
Sys Clk Low Pulse
CCLK0 Cycle Time
CCLK1 Cycle Time
CCLK2 Cycle Time
CCLK3 Cycle Time
CCLK4 Cycle Time
CCLK5 Cycle Time
CCLK6 Cycle Time
CCLK7 Cycle Time
CCLKm High Time
CCLKm Low Time
MIN
1X CLK MODE
5.0
4.3
45
45
40%
40%
Unused clocks should be pulled to a known state (ground) through a resistor. If you are
using a clock generator, disabling the output should not cause a tristate. If it does, then
the line should be pulled down.
This section describes the timing for the following CP interfaces:
•
•
•
•
DS1/DS3 Ethernet Timing Description
10/100 Ethernet Timing Description
Gigabit GMII/MII Ethernet Interface Timing Description
OC-3 Timing Description
2X CLK MODE
3.0
2.5
2.14
30
30
40%
40%
TYP
647.67
488.28
29.097
22.353
20.00
9.412
8.00
6.43
MAX
1X CLK MODE
55
55
60%
60%
2X CLK MODE
70
70
60%
60%
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
COMMENT
166MHz core clock
200MHz core clock
233MHz core clock
Duty cycle*
Duty cycle†
T1†
E1†
E3†
T3†
RMII†
Fibre Channel†
GMII†
OC-3†
% cycle pulse is high
% cycle pulse is low