MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 44

• Manufacturer Part Number: MCC501RX200TD0B
• Manufacturer: Freescale Semiconductor

Specifications of MCC501RX200TD0B

• Package Type: BGA
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

44
Table 17 General System Interface Signal
Fabric Processor Interface
Table 18 Fabric Interface Signals
C5NP
SIGNAL NAME
XPUHOT
TOTAL PINS
SIGNAL NAME
FIN0 - FIN31
FOUT0 - FOUT31
FRXCLK
FTXCLK
FRXCTL0 - FRXCTL6
CHAPTER 2: SIGNAL DESCRIPTIONS
PIN #
J19
Signals
PIN #
W2, V1, T1, V2, U2, V3, T3, T2, W4, V4, V5, U4, T4,
W6, V6, U6, T5, T6, V7, T7, X8, W8, V8, V9, U8, X9,
V10, U10, X10, W10, X11, V11
W28, V29, T29, V28, U28, V27, T27, T28, W26,
V26, V25, U26, T26, W24, V24, U24, T25, T24,
V23, T23, X22, W22, V22, V21, U22, X21, V20,
U20, X20, W20, X19, V19
W14
W16
U12, W12, V12, X12, X13, V13, X14
TOTAL
1
1
The FP consists of two logical signal interfaces: a receive data interface and a transmit
data interface, each with its own control and clocking signals. The interface has the
following characteristics:
•
•
Each data bus can be run at widths of 16 or 32 bits of data (FIN0 - FIN31 and FOUT0 -
FOUT31) per clock. The extra data pins in each configuration remain unused. The output
pins are driven to a known state, and the input pins should also be pulled to a known
state.
TYPE
LVTTL
The interface clocks FRXCLK and FTXCLK can have a different frequency from the core
C-5 NP clock frequency. The Fabric Data Processor (FDP) has synchronizing FIFOs at its
interface boundary to allow for a fabric interface frequency from 10MHz to 110MHz.
The receive clock FRXCLK and the transmit clock FTXCLK must share the same
frequency. The synchronization logic internal to the FP requires related clock domains
on the transmit and receive interfaces. Each of the two clocks can have different phase
alignment, however, because they are generated externally.
I/O
I
SIGNAL DESCRIPTION
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low
equals reset and High equals active. During normal operation, this is an
external interrupt.
TOTAL
32
32
1
1
7
TYPE
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O
I
O
I
I
I, O
SIGNAL DESCRIPTION
Fabric Data Bus In
Fabric Data Bus Out
Receive Clock
Transmit Clock
Receive Control Signals