MCC501RX200TD0B Freescale Semiconductor, MCC501RX200TD0B Datasheet - Page 35

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MCC501RX200TD0B

Manufacturer Part Number
MCC501RX200TD0B
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MCC501RX200TD0B

Package Type
BGA
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MCC501RX200TD0B
Manufacturer:
FREESCALE
Quantity:
20 000
Table 10 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
*
SIGNAL NAME*
CPn+1_4
CPn+1_5
CPn+1_6
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
CPn+3_0
CPn+3_1
CPn+3_2
CPn+3_3
CPn+3_4
CPn+3_5
CPn+3_6
TOTAL PINS
n can be 0, 4, 8, or 12.
Reference
Table 6
for pin numbers for the actual cluster(s) you are configuring.
PIN #†
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
Table 6
TOTAL
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
28
Gigabit Ethernet and Fibre Channel TBI Configuration
1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same
way as Gigabit Ethernet (GMII).
TYPE
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O
O
O
O
I
I
I
I
I
I
nc
I
I
I
I
I
I
LABEL
TXD(6)
TXD(7)
TX_ER
nc
RCLK
RXD(0)
RXD(1)
RXD(2)
RXD(3)
RX_DV
nc
CRS
RXD(4)
RXD(5)
RXD(6)
RXD(7)
RX_ER
SIGNAL DESCRIPTION
Transmit Data
Transmit Data (byte-wide receive data, most significant bit)
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes
transmission of the designated “bad code” in lieu of the normal
encoded data on the twisted pair data.
nc
Receive Clock (125MHz)
Receive Data (byte-wide receive data, least significant bit)
Receive Data
Receive Data
Receive Data
Receive Data Valid. Indicates that there is a receive frame in progress
and that the data present on the RXD signals is valid.
nc
Carrier Sense. Indicates traffic is on the link. CRS is asserted when a
non-idle condition is detected on the receive data stream. CRS is
deasserted when an end of frame or idle condition is detected.
Receive Data
Receive Data
Receive Data
Receive Data (most significant bit)
Receive Error Detected. Indicates that there has been an error
received in the receive frame.
Table 9
shows the possible CP pin combinations you can
Pin Descriptions Grouped by Function
V 04
35

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