PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 40
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PEF2054NV21XK
Manufacturer Part Number
PEF2054NV21XK
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF2054NV21XK.pdf
(269 pages)
Specifications of PEF2054NV21XK
Lead Free Status / Rohs Status
Compliant
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Figure 19
Pre-processed Channel Codes
To program a pair of pre-processed channels the correct code for the selected handling
scheme must be written to the CM. Figure 19 gives an overview of the available pre-
processing codes and their application. For further detail, please refer to chapter 5.5.
Semiconductor Group
m
- : Inactive sub. time-slot, in downstream direction these bits are tristated (OMDR : COS
C/I : Command/Indication channel, these bits are exchanged between the CFI in/output and the CM data field. A change of
D : D channel, these D channel bits are transparently switched to and from the PCM interface.
SIG : Signaling Channel, these bits are exchanged between the CFI in/output and the CM data field. The SIG value which
actual value
stable value
value in upstream direction causes an interrupt (ISTA : CFI). The address of the change is stored in the CIFIFO.
DD Application
DD
: Monitor channel bits, these bits are treated by the monitor/feature control handler
Decentral
D Channel
Handling
Central
D Channel
Handling
Signaling
(e.g. analog
Signaling
(e.g. SLD)
6
8 Bit
Decentral
D Channel
Handling
Central
D Channel
Handling
6
Signaling
(e.g. analog
IOM
8
Signaling
(e.g. SLD)
IOM )
Bit
Bit
Bit
Application
the C/I bits in upstream direction causes an interrupt
R
R
)
was present in the last frame is stored as the actual value in the even address CM location. The stable value is updated
if a valid change in the actual value has been detected according to the last look algorithm. A change of the SIG stable
1
1 0 0 0
1
1 0 1 1
1 0 0 0
1
1 0 1 0
1
Even Control Memory Address
MAAR = 0......0
Code Field
MACR
Even Control Memory Address
MAAR
Code Field
MACR
0
0
0
0
0
1
1
1
= 1......0
=
=
0
0
0
0
0111...
0111...
SIG Actual Value
1
1 1
1 1
1
SIG Actual Value
1
1
SIG
Data Field
MADR
Data Field
MADR =
SIG
C/I
C/I
C/I
C/I
=
......
......
X
1
1
1
1
1 1
X
1
1
1
1
(ISTA
PCM Code for
PCM Code for
0 0 0 0
2 a
Time-Slot
a Bit Sub.
Time-Slot
1
1
: SFI). The address of the change is stored in the CIFIFO
1
1 0 1 1
1 0 1 1
Odd Control Memory Address
MAAR
Code Field
MACR
2
Odd Control Memory Address
MAAR
Code Field
MACR
Bit
0
0
0
Sub.
1
1
1
=
=
= 0111...
=
0
1
1
0......1
1......1
0111...
SIG
X X
X
X X
X X
40
Pointer to a PCM Time-Slot
Pointer to a PCM Time-Slot
SIG
X
Stable
X X
X
X X
X X
Stable
Data Field
MADR =
Data Field
MADR ......
= 0)
X
Value
X X
X
X X
X X
or set to logical 1
Value
X
=
......
X
X X
X
X
X
X
X
X
X
Feature
Feature
(OMDR
Even Time-Slot
Even Time-Slot
m m
m
m m
m m
m m
m m
m m
m m m m m m m m
Monitor Channel
Monitor Channel
Monitor Channel
Monitor Channel
Monitor Channel
Monitor Channel
m
Downstream Preprocessed Channels
Input from the Configurable Interface
Output at the Configurable Interface
m
m
m
m
m
m
m
Upstream Preprocessed Channels
Operational Description
:
Control
Control Channel
COS
m m m m
m
m m m m
m m m m
m m m m
m m m m
m m m m
m
=
m
1)
Channel
m
m
m
m
m
m
m
m
D
D D
-
- -
Signaling Channel
Signaling Channel
Control Channel
Control Channel
Control Channel
Control Channel
Control Channel
Control Channel
D
-
SIG
SIG
Odd Time-Slot
Odd Time-Slot
SIG
SIG
C/I
C/I
C/I
C/I
PEB 2055
PEF 2055
m m
m
m m
m m
m
m m
m
m
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