PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 220
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PEF2054NV21XK
Manufacturer Part Number
PEF2054NV21XK
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF2054NV21XK.pdf
(269 pages)
Specifications of PEF2054NV21XK
Lead Free Status / Rohs Status
Compliant
- Current page: 220 of 269
- Download datasheet (2Mb)
2) In PCM mode 0 and CFI mode 0, the P shall have access to both the downstream
Wait for next SIN interrupt and transfer further data bytes … .
Examples
1) In PCM mode 0, the synchronous transfer utility (channel A) shall be used to loop
Semiconductor Group
bits 7 … 6 of downstream PCM port 1, time slot 5 back to bits 7 … 6 of upstream
PCM port 2, time slot 9. Since no P access to the data is required the ISTA:SIN and
SOV bits are both masked:
W:MASK
W:SARA
W:SAXA
W:STCR
and upstream CFI port 0, time slot 1 via the synchronous transfer channel B:
W:SARB
W:SAXB
W:STCR
Wait for interrupt:
R:ISTA
R:STDB
W:STDB
= 03
= 13
= 25
= 47
= 81
= 81
= 88
= 02
= upstream CFI data
= downstream CFI data
H
H
H
H
H
H
H
H
; SIN = SOV = 1
; ISRA = 0, port 1, TS5
; ISXA = 0, port 2, TS9
; TAE = 1, CTA2 … 0 = 111 (bits 7 … 6)
; ISRB = 1, port 0, TS1
; ISXB = 1, port 0, TS1
; TBE = 1, CTA2 … 0 = 001 (bits 7 … 0)
; SIN = 1
220
Application Hints
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