PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 107
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PEF2054NV21XK
Manufacturer Part Number
PEF2054NV21XK
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF2054NV21XK.pdf
(269 pages)
Specifications of PEF2054NV21XK
Lead Free Status / Rohs Status
Compliant
- Current page: 107 of 269
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CFI Clock Source Prescaler CMD1:CSP1 … 0
The CFI clock source PDC (CMD1:CSS = 0) or DCL (CMD1:CSS = 1) can be divided by
a factor of 1, 1.5 or 2 in order to obtain the CFI reference clock CRCL (see table 16).
Note that in CFI mode 2, the frequency of RCL is only half the CFI data rate.
Table 16
CSP1
0
0
1
1
Figure 31
EPIC
Semiconductor Group
DCL
FSC
®
Clock Sources for the CFI and PCM Interfaces if CMD1:CSS = 1
C
F
I
Bit Shift
CTAR
CBSR: CDS2...0
CFI Frame Sync.
CFI Data Rate
1.5
2
CMD
: CSP1,
M
U
X
0
CRCL
CSP0
0
1
0
1
2
2
4
CFI Mode
CFI Mode
2
0
3
2
0
3
1
1
EPIC
107
Internal Reference
Clock (RCL)
R
Bit Shift
POFU
POFD
PCSR
Prescaler Divisor
2
1.5
1
not allowed
PCM Frame Sync.
PCM Data Rate
PMOD
M
U
X
: PCR
Application Hints
2
PEB 2055
PEF 2055
ITS09548
M
P
C
PDC
PFS
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