PEF2054NV21XK Infineon Technologies, PEF2054NV21XK Datasheet - Page 11

• Manufacturer Part Number: PEF2054NV21XK
• Manufacturer: Infineon Technologies

Specifications of PEF2054NV21XK

• Lead Free Status / Rohs Status: Compliant

28
44
16
1.3
EPIC-S EPIC
30
29
19
20
21
22
23
24
25
26
31
32
Semiconductor Group
Pin No.
30
29
28
19
20
21
22
23
24
25
26
31
32
44
16
Pin Definitions and Functions
Symbol Input (I)
CS
WR,
R/W
RD, DS I
AD0, D0
AD1, D1
AD2, D2
AD3, D3
AD4, D4
AD5, D5
AD6, D6
AD7, D7
ALE
INT
RES
PFS
Output (O)
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
(OD)
I
I
Function
Chip Select; active low. A “low” on this line
selects the EPIC for read/write operations.
Write, active low, Siemens/Intel bus mode.
When “low”, a write operation is indicated.
Read/Write, Motorola bus mode.
When “high” a valid P-access identifies a read
operation, when “low” it identifies a write access.
Read, active low, Siemens/Intel bus mode.
When “low” a read operation is indicated.
Data Strobe, Motorola bus mode.
A rising edge marks the end of a read or write
operation.
Address/Data Bus; multiplexed bus mode.
Transfers addresses from the P-system to the
EPIC and data between the P and the EPIC.
Data Bus; demultiplexed bus mode.
Transfers data between the P and the EPIC.
When driving data the pins have push pull
characteristic, otherwise they are in high
impedance state.
Address Latch Enable
ALE controls the on chip address latch in
multiplexed bus mode. While ALE is “high”, the
latch is transparent. The falling edge latches the
current address. During the first read/write
access following reset ALE is evaluated to select
the bus mode.
Interrupt Request, active low.
This signal is activated when the EPIC requests
an interrupt. Due to the open drain (OD)
characteristic of INT multiple interrupt sources
can be connected together.
Reset
A “high” forces the EPIC into reset state.
PCM Interface Frames Synchronization
11
PEB 2055
PEF 2055
Overview