82V2608BB IDT, Integrated Device Technology Inc, 82V2608BB Datasheet - Page 12

• Manufacturer Part Number: 82V2608BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2608BB

• Utopia Level: Level 2
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: BGA
• Pin Count: 208
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table-1 Pin Description
2
IDT82V2608
PIN DESCRIPTION
SYSCLK
TxAddr4
TxAddr3
TxAddr2
TxAddr1
TxAddr0
TxData7
TxData6
TxData5
TxData4
TxData3
TxData2
TxData1
TxData0
TxClav
TxSOC
RxEnb
TxEnb
RxClk
Name
TxClk
RST
PIN DESCRIPTION
Pin Number
R11
G14
G15
G16
H14
H15
H16
D16
D15
E14
F15
F14
F13
E16
E15
E13
F16
J16
J15
J14
E4
Input/Output
High-Z
O
I
I
I
I
I
I
I
I
I
SYSCLK: System Clock
System clock for the IDT82V2608. Default is 20 MHz.
RST: System Reset
System reset signal, low active. After reset, all registers are reset to default values, and both the con-
tents in SRAM and the downloaded software are cleared.
TxClk: Utopia Transmit Clock
Utopia transmit clock used to transfer data from the ATM layer to the IDT82V2608. The frequency of
the TxClk should be less than or equal to that of the system clock.
Data is sampled on the rising edge of this signal.
TxEnb: Utopia Transmit Enable
Utopia low active signal asserted by the ATM layer device during cycles when TxData contains valid
cell data.
The TxEnb input is sampled on the rising edge of TxClk.
TxAddr[4:0]: Utopia Transmit Address
Utopia transmit port address driven from the ATM layer to poll and select an appropriate port.
The TxAddr[4:0] input bus are sampled on the rising edge of TxClk.
TxData[7:0]: Utopia Transmit Data
Utopia 8-bit data bus driven from the ATM layer to the IDT82V2608.
The TxData[7:0] input bus are sampled on the rising edge of TxClk.
TxClav: Utopia Transmit Cell Available
Utopia transmit cell available signal from the IDT82V2608 to the ATM layer. A polled port drives TxClav
only during each cycle following one with its address on the TxAddr lines. The polled port asserts
TxClav high to indicate its corresponding FIFO can accept the transfer of a complete cell, otherwise it
deasserts the signal.
The TxClav output is updated on the rising edge of TxClk.
Note: This pin requires a pull-down resistor.
TxSOC: Utopia Transmit Start of Cell
Utopia start of cell signal. It will be driven high by the ATM layer when TxData[7:0] contain the first valid
byte of a cell.
The TxSOC input is sampled on the rising edge of TxClk.
RxClk: Utopia Receive Clock
Utopia receive clock. The frequency of RxClk should be less than or equal to the frequency of the sys-
tem clock.
Data is sampled on the rising edge of this signal.
RxEnb: Utopia Receive Enable
When this pin is low, the received data will be transferred on RxData[7:0] in the following cycles.
The RxEnb input is sampled on the rising edge of RxClk.
ATM Utopia Interface
Global Signals
12
Description
Inverse Multiplexing for ATM
December 4, 2006