EVAL-ADF7010EB1 Analog Devices Inc, EVAL-ADF7010EB1 Datasheet - Page 8

• Manufacturer Part Number: EVAL-ADF7010EB1
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF7010EB1

• Lead Free Status / Rohs Status: Not Compliant

Designing Loop Filters with ADIsimPLL
The design of a loop filter for a PLL based transmitter
is crucial to its performance. For an FSK based system
it determines how quickly the jump from frequency 1 to
frequency 2 can be made. In a frequency hopping sys-
tem it determines how much time is 'wasted' when
jumping from one hopping frequency to another. Often
we use as wide a bandwidth as possible while still meet-
ing FCC regulations. A good 'rule-of-thumb' is 5 to10
times the datarate. (e.g. 19.2kbits/s datarate requires a
100kHz Loop BW).
For an ASK based system, there will be some 'pulling'
of the VCO when a significant output level changes
occurs when the data transitions between a mark and a
space. To minimise this, a wide loop BW (300kHz)
should be designed even for lower datarates, to pull the
output frequency back to the correct value quickly.
ADIsimPLL can be found on the Evaluation CD. This
allows simple accuarate design of loop filters with real
components in several configurations. The next version
will have several additonal functions for ADF7010
users.
E
FSK based frequency hopping system
Designed to meet FCC 15.247
Datarate
Crystal
Requires
The 'rule-of-thumb' of loop filter BW points being 5-10
times the datarate.
Desired Loop BW
Increasing the phase margin damps the response and so
reduces the overshoot resulting in a better FSK spec-
trum.
Desired phase margin
The charge pump current should be set to 2.02mA to
optimise noise performance. Normally the effects are
negligible. Some users may wish to set the charge
pump current to ICPmax / 2, so they can switch the
current to ICPmax when jumping from one frequency
to another to temperoraily increase the loop BW and
reduce settling time. The gains are not significant.
Icp
The PFD frequency should be chosen to be a max.
There are 2 good reasons for this. The bigger the PFD
frequency - the less the multiplication factor (N) to the
output frequency. Since phase noise is multiplied up by
20 log N, doubling the N will degrade phase noise by
3dB's.
The 2nd reason is to minimise integer boundary spurs.
XAMPLE
D
ESIGN
19.2kbits/s
19.2MHz AT
50 Hopping Channels
100kHz
60 degrees
2.02mA
–VIII–
Integer boundary spurs are created when the fractional
value is either near zero or near the max F. These
spurs in-band are typically of the order of -25dBc. By
avoiding fractions near integers, the spurious are re-
duced to < 45dBc at 1MHz offset with a 100kHz loop
filter. Higher PFD frequencies create fewer of these
integer channels in the desired band, therefore reduce
the occurances of integer boundary spurs.
PFD frequency
The VCO on the ADF7010 is internal. The tuning
sensitivity plots (Kv) are shown in the datasheet. As the
Kv increases so does the loop BW. A Kv of 80MHz/V
at 915MHz is typical.
Kv
Designing the loop filter - ADIsimPLL
Run ADIsimPLL
1) Select 'Create a new PLL design'
2) Choose Output Frequency in the desired range.
Min Frequency
Max Frequency
Channel spacing is 400kHz (50 x 400kHz = 20MHz)
3) Select Fractional-N - Use the default Frac-N which
is the ADF4252_RF
Select Fractionality = 48
4) Select custom VCO and set Kv = 80MHz/V
5) Select custom reference (crystal) = 19.2MHz
6) Use the next key to select the loop filter with an
extra RC for spurious attenuation. This is a 3rd order
integrator and is ideal for Frac-N designs.
7) Click Finish to see the simulation
8) On the left hand side of page, expand the chip and
make Rset = 5.6k. Icp = 2.1mA which is close to our
actual Icp.
9) Expand the loop filter section. Set the Loop BW to
100kHz. Set the phase margin to 60 degrees.
10) Click on 'Tools' on the top menu and 'Build' to
generate the loop filter from real capacitor and resistor
values.
EVAL-ADF7010EB1
19.2MHz
80MHz/V
902MHz
928MHz
REV.PrB 07/02