EVAL-ADF7010EB1 Analog Devices Inc, EVAL-ADF7010EB1 Datasheet
EVAL-ADF7010EB1
Specifications of EVAL-ADF7010EB1
EVAL-ADF7010EB1 Summary of contents
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... DVDD Chip Enable Output Matching ADF7010 CLK, DATA, LE 19.2MHz AT Cut TxCLK One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781-329-4700 ADF7010 RF Transmitter Evaluation Board EVAL-ADF7010EB1 RFout Harmonic Filter CLKout Crystal REV.PrB 07/02 © Analog Devices, Inc., 2002 Fax: 781-326-8703 ...
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... DC level exists at the RFout SMA - DC into the front of measurement equipment will damage the input. There is a 150pF ac coupling capacitor at the output. The parallel port has 5V voltage levels, so there is a volt- age divider to bring this down to levels acceptable to the ADF7010. EVAL-ADF7010EB1 EVAL-ADF7010 ...
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... Figure 3. Evaluation Board Circuit Diagram (Page 1) –III– EVAL-ADF7010EB1 REV.PrB 07/02 ...
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... The initial offset in the crystal will cause the absolute output frequency to be off. This error can be calibrated out using the fractional-N registers. Figure 4 Software Front Panel Display –IV– EVAL-ADF7010EB1 REV.PrB 07/02 ...
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... The phase noise is measured by moving to a 10kHz span on the spectrum analyser, and setting the marker delta at 2kHz. Turn marker noise on. A typical measurment for 0dBm output power is -80dBc/Hz. – V – EVAL-ADF7010EB1 Increased output REV.PrB 07/02 ...
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... Lock Detect signal goes high therefore a good idea to wait for Lock Detect signal to go high before enabling the output stage to ensure there are no unwanted tranmissions at incorrect frequencies while the PLL is attempting to lock. –VI– EVAL-ADF7010EB1 Spectrum Analyser CLKout Lock Detect REV.PrB 07/02 ...
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... PFD (Phase Frequency Detector). The ADF7010 features a Digital Lock Detect which goes high at MUXout when the PLL is locked. EVAL-ADF7010EB1 The total start-up time is typically 1.2ms for 3V operation with a 40kHz loop BW. Start-up time for ADF7010 from Function Latch being ...
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... Expand the loop filter section. Set the Loop BW to 100kHz. Set the phase margin to 60 degrees. 10) Click on 'Tools' on the top menu and 'Build' to generate the loop filter from real capacitor and resistor values. –VIII– EVAL-ADF7010EB1 19.2MHz 80MHz/V 902MHz 928MHz REV.PrB 07/02 ...
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... GFSK is useful where the spectral occupancy is crucial. It requires some extra design work, as the data most be clocked into the ADF7010 at a constant rate. EVAL-ADF7010EB1 The bits designated for GFSK are in the modulation reg- ister. To decide on what these should be set to, the fol- lowing are required ...
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... Figure 8. TxCLK signal provided at 18.75kHz. The micro or shift register should use the posi- tive edge to clock the data from its buffer to the TxData pin of the ADF7010. The delay al- lowed is 26.6us in this case at the 7010 will sample on the negative edge of the signal. 53.3 US 26.6 ADF7010 US SAMPLES DATA HERE – X – EVAL-ADF7010EB1 REV.PrB 07/02 ...
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... C20 C21 4 Stick-on Feet Each Corner LOOP FILTER COMPONENTS 1 1.5nF C1 1 33nF C2 1 270pF C3 1 180R R1 1 910R R2 EVAL-ADF7010EB1 TSSOP24 DB9-HM SMA_CARD_EDGE_RF J502-ND SMA SMA HC49 SW-SP3T-SLIDE SIP-2P TESTPOINT Coilcraft 603CS_12NX_BC Coilcraft 603CS_6N8X_BC 603 603 603 603 603 603 805 603 ...