EVAL-ADF7010EB1 Analog Devices Inc, EVAL-ADF7010EB1 Datasheet - Page 5

• Manufacturer Part Number: EVAL-ADF7010EB1
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF7010EB1

• Lead Free Status / Rohs Status: Not Compliant

The evaluation performed will be specific to each
application, but this section will enable to user to
familiarise themselves with the features of the
ADF7010.
Initial Set-up
The board will be set-up will RFVdd and CPVdd tied
to the DVDD supply. Set this to 3V, and use a current
meter to monitor the supply current. With Chip Enable
(low) the part will be set to its default condition as
goverened by the values preset internally in the
registers. There will be no current drawn. Once CE is
brought high the part will become active and approxi-
mately 0.8mA is drawn.
Crystal Oscillator circuit
CLKout
CLKout Divide
PLL
PA
Data Invert
M u x O U T
For the user, this means that there will be a signal at
19.2MHz / 16 at the CLKout pin, and also that the
crystal oscillator is running.
Programming the ADF7010
Programming is accomplished using the parallel port of
the PC. The interface is SPI compatible, and the LPT1
levels are divided down to make them compatible with
the lower Vdd of the transmitter. The programming
lines are pulled low internally once programming has
been completed. This is important as the parallel port
can source current to the part if it's 'high' voltage is at a
higher level than the Vdd of the ADF7010.
Setting the output frequency
The output frequency is set by the PFD (Phase
Frequency Detector) frequency x by the N divider
value. The default setting for the PFD is 19.2MHz.
This is accomplished by setting the R-divider to 1. The
N value is comprised of an integer and fractional part.
The output frequency is -
PFD frequency x (Int +
So 19.2MHz * (47 + 2752 / 2^15) = 915.3MHz
In this case the integer register contains 47 and the
Fractional register is set to 2752.
G
ETTING STARTED WITH THE
-------------------------------
(2
3
x Fractional) + Error )
O N
O N
16 ( 8 x 2)
O F F
O F F
O F F
Regulator Ready
ADF7010
2
15
– V –
Test Procedure for the ADF7010
Use a supply of 3V to power the part. Monitor the current
using an ammeter.
1. Set CE high using the switch. Ensure that all jumpers
on the board are tied together. The current drawn should
be <1uA. This is the standby current.
2. Monitor the CLKout pin using a scope. The output
frequency once CE is high is 19.2MHz / 16. This is the
power-up default. The crystal is oscillating and the
CLKout feature is working.
3. Set the output frequency to the desired frequency using
the evalutation software. Hit the calculate and load now
buttons to see what N and R values are written and to load
the ADF7010 N and R registers.
4. Return to the main menu. Select OOK modulation, and
set Data Invert to 1. This will put the part in PLL mode
with the output power selectable by changing the power
level. Update the Modulation and Function register.
5. Examine the output using a spectrum analyser. The
output should be locked to the programmed output
frequency (There will be some error associated with the
crystal). You can change the output level by adjusting the
output power in the OOK window.
6. Re-Enter the 'set frequency' menu and change the
output frequency and verify it covers your required
frequency range.
7. Phase Noise and Spurious
The ADF7010 can operate in both in integer and
fractional PLL modes. When the part is in ASK or OOK
mode and the fraction is zero then the part is in integer
mode and the sigma-delta is powered down.
In FSK and ASK (with F >0) the sigma delta is on and
the output can be changed in steps of PFD/2^12. To
measure the spurious set the Marker to peak search and
locate the carrier. Using the marker delta function on the
spectrum analyser set the next highest peak. In integer
mode the spurious components will be at Carrier + Fpfd,
Carrier + 2Fpfd, etc. In fractional mode the spurs will be
at pfd * fraction and its harmonics. e.g. If the fractional
register is 2048, and the fraction is 1/2, then there will be
a fractional spur at Fpfd / 2. The loop filter will
significantly attenuate fractional spurs, that are at a
frequency many times the loop BW, away from the carrier.
It is for this reason that 19.2MHz is chosen as the crystal
reference as it allows most channel spacings (30kHz,
40kHz, 100kHz,400kHz) to be divided into it easily. This
results in bigger fractions, and spurious that are well
attenuated by the loop filter.
The phase noise is measured by moving to a 10kHz span
on the spectrum analyser, and setting the marker delta at
2kHz. Turn marker noise on. A typical measurment for
0dBm output power is -80dBc/Hz.
EVAL-ADF7010EB1
Increased output
REV.PrB 07/02