EVAL-ADF7010EB1 Analog Devices Inc, EVAL-ADF7010EB1 Datasheet - Page 6

• Manufacturer Part Number: EVAL-ADF7010EB1
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF7010EB1

• Lead Free Status / Rohs Status: Not Compliant

The MUXout feature is very useful in the debug and sys-
tem use of the ADF7010. It allows access to internal sec-
tions of the IC such as the R-divider and N-divider
outputs. The R-divider/2 can be used to check that the
crystal oscillator is working, and that the R-divider is
dividing the crystal frequency down to the Fpfd as
expected. For the evaluation board, the crystal is chosen
as 19.2MHz and the PFD is at 19.2 MHz. The R-divider/
2 output will look like a 9.6MHz square wave. When the
PLL is locked, the N-divider output will be in phase and
at the same frequency as the R-divider. This can be
verified by setting the MUXout to N-divider / 2. The
result should be a 9.6MHz square wave.
Regulator Ready - The ADF7010 goes into complete
powerdown when Chip Enable (CE) is brought low. The
values in the registers are lost and the serial interface is
disabled. When CE is brought high there is a delay before
the regulator voltage settles to the correct level (2.2V). By
default the MUXout is set to regulator ready. When CE is
brought high the MicroController must wait until the
regulator ready (reg_ready) signal is high (at MUXout)
before the ADF7010 can be programmed.
power
phase noise at +9.6dBm is -73dBc/Hz.
Signal Generator
will result in an increased noise floor. Typical
TxData
Ammeter
MUXout feature
3.00V
Voltage Supply
Evaluation
ADF7010
MUXout
Board
CLKout
Figure 4. Evaluation Board Test Setup
RFout
–VI–
The part is initialised by programming each of the 4
registers. Usually, MUXout is set to Lock Detect (Digital).
There is a delay associated with the VCO being enabled
and also the loop has to settle to the output frequency as
defined by the N and R-registers. Once the part is locked
to the correct frequency the Lock Detect signal goes high.
It is therefore a good idea to wait for Lock Detect signal to go
high before enabling the output stage to ensure there are no
unwanted tranmissions at incorrect frequencies while the PLL
is attempting to lock.
Oscilloscope
Lock Detect
CLKout
Spectrum Analyser
EVAL-ADF7010EB1
REV.PrB 07/02