EVAL-ADF7010EB1 Analog Devices Inc, EVAL-ADF7010EB1 Datasheet - Page 7

• Manufacturer Part Number: EVAL-ADF7010EB1
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF7010EB1

• Lead Free Status / Rohs Status: Not Compliant

Regulator start-up time = 300us, Vdd = 3V, Creg = 4.7uF
The crystal oscillator (enabled by default) needs to power
up. This is determined by the Q of the crystal, and the
supply voltage. A CLKout signal will appear at Fcrystal /
16 at the CLKout pin, once the oscillation has reached
sufficient threshold to trigger the R-divider.
Crystal start-up time = 460us, Vdd = 3V, Xtal AT
19.2MHz.
2. The PLL and VCO also have an associated power-up
time.Once the VCO is active (70us approximately), the
PLL will attempt to lock. This will occur when the N-
divider output and the R-divider output are at frequency
and phase locked at the PFD (Phase Frequency Detector).
The ADF7010 features a Digital Lock Detect which goes
high at MUXout when the PLL is locked.
Start-up Procedure
There is specified start-up time/sequence from the CE
going high to the ADF7010 being ready to transmit
1. The regulator works at a nominal voltage of 2.2V. It
supplies the reference voltage to the serial interface and
most blocks of the tranmitter. Due to the large Creg
capacitor, there is a settling transient associated with
this. Before the part can be programmed the regulator
voltage must have settled. This can be monitored by the
default condition on MUXout (reg_ready).
–VII–
The total start-up time is typically 1.2ms for 3V operation
with a 40kHz loop BW.
Start-up time for ADF7010 from Function Latch being
programmed to Lock Detect going high, Vdd = 3V
The Lock Detect should be monitored then to determine
when it is OK to transmit. However there is a delay
between the Lock Detect and when the PLL is locked to
1ppm.
This is shown below for a 12.4MHz jump. The Lock
Detect shows a locked PLL at 42us. The actual lock
time to 1ppm is 50% more than this. This can be used as
a rule of thumb for frequency to frequency lock. For a
start-up locked condition it is relatively much less.
The lock time as given by the Digital Lock Detect from
MUXout shows a 40us jump time for a 12MHz jump. The
actual lock time is 65us as shown from the Modulation
Domain Analyser.
EVAL-ADF7010EB1
REV.PrB 07/02