EVAL-ADF7010EB1 Analog Devices Inc, EVAL-ADF7010EB1 Datasheet - Page 10

no-image

EVAL-ADF7010EB1

Manufacturer Part Number
EVAL-ADF7010EB1
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADF7010EB1

Lead Free Status / Rohs Status
Not Compliant
EVAL-ADF7010EB1
53.3
US
M
C
ICRO
O NTRO LLER SHOULD CLOCK
DATA OUT ON THE POSITIVE EDGE
26.6
ADF7010
US
SAMPLES DATA HERE
Figure 8. TxCLK signal provided at 18.75kHz. The micro or shift register should use the posi-
tive edge to clock the data from its buffer to the TxData pin of the ADF7010. The delay al-
lowed is 26.6us in this case at the 7010 will sample on the negative edge of the signal.
REV.PrB 07/02
– X –