ANXL1500FGC3M AMD (ADVANCED MICRO DEVICES), ANXL1500FGC3M Datasheet - Page 42

• Manufacturer Part Number: ANXL1500FGC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXL1500FGC3M

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.3
The processor implements a Clock Control (CLK_CTL)
MSR (MSR C001_001Bh) that determines the internal
clock divisor when the AMD processor system bus is dis-
connected.
Refer to the AMD Geode™ NX Processors BIOS Consider-
ations Application Note (publication ID 32483) and the
BIOS Requirements for BIOS Requirements for AMD Pow-
erNow™ Technology Application Note (publication ID
25264) for more details on the CLK_CTL register.
3.4
The processor provides two mechanisms for communicat-
ing processor core operating frequency information to the
Northbridge. These are the processor FID[3:0] outputs and
the FID_Change special cycle. The FID[3:0] outputs spec-
ify the core frequency of the processor as a multiple of the
input clock (SYSCLK/SYSCLK#) of the processor. This
processor supports an input clock, or Front Side Bus
(FSB), that runs up to 133 MHz.
The FID[3:0] signals are valid after PWROK is asserted.
The chipset must not sample the FID[3:0] signals until they
become valid. The FID[3:0] outputs of the processor pro-
vide processor operating frequency information the North-
bridge uses when creating the SIP stream the Northbridge
sends to the processor after RESET# is de-asserted. The
FID[3:0] outputs always select a 6x SYSCLK multiplier for
the Geode NX processor: FID[3:0] = 0110.
Software uses the FID_Change protocol to transition the
processor to the desired performance state.
42
Clock Control
SYSCLK Multipliers
31177H
The FID[3:0] outputs are not used as part of the
FID_Change protocol and do not change from their
RESET# value during software-controlled processor core
frequency transitions.
The FID_Change special cycle is used to communicate
processor operating frequency information to the North-
bridge during software-controlled processor core voltage
and frequency (performance state) transitions. The
FidVidCtl MSR (MSR C001_0041h) allows software to
specify a 5-bit FID value during software-controlled proces-
sor performance state transitions. The additional bit allows
transitions to lower SYSCLK multipliers of 3x and 4x as
well as all other SYSCLK multipliers supported by the pro-
cessor.
For a description of the FID_Change protocol refer Section
3.1.5 on page 35.
Table 3-1 lists the FID[4:0] SYSCLK multiplier codes for the
processor used by software to dictate the core frequency of
the processor and the 5-bit value driven on SDATA[36:32]#
by the processor during the FID_Change special bus cycle.
Note: Only clock multipliers associated with operating
frequencies specified in Section 5.0 "Electrical
Specifications" on page 47 are valid for this pro-
cessor. Software distinguishes the speed grade of
the processor by reading the MFID field of the Fid-
VidStatus MSR (MSR C001_0042h).
AMD Geode™ NX Processors Data Book
Power Management