ANXL1500FGC3M AMD (ADVANCED MICRO DEVICES), ANXL1500FGC3M Datasheet - Page 36

• Manufacturer Part Number: ANXL1500FGC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXL1500FGC3M

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.1.6.1
In any FID_Change transition, only the core voltage or core
frequency
FID_Change transitions are required to transition the volt-
age and frequency to a valid performance state. When the
voltage is being transitioned, the frequency is held constant
by transitioning to the same FID[3:0] as the current FID
reported in the FidVidStatus MSR (MSR C001_0042h).
Example
1)
2)
3)
4)
5)
6)
On the instruction boundary that the SGTC field of the
FidVidCtl MSR is written to a non-zero value, the processor
stops code execution and issues a FID_Change special
cycle on the AMD processor system bus.
The FID_Change special cycle has a data encoding of
0007_0002h that is passed on SDATA[31:0].
SDATA[36:32] contain the new FID[4:0] code during the
FID_Change special cycle. The Northbridge is required to
capture this FID[4:0] code when the FID_Change special
cycle is run.
36
System software determines that a change in proces-
sor performance state is required.
System software executes a WRMSR instruction to
write to the FidVidCtl MSR (MSR C001_0041h) to dic-
tate:
The FIDCHGRATIO bit (MSR C001_0041h[20]) must
be set to 1.
The VIDC bit (MSR C001_0041h[17]) must be set to 1
if the voltage is going to be changed.
The FIDC bit (MSR C001_0041h[16]) must be set to 1
if the frequency is going to be changed.
Writing the SGTC field (MSR C001_0041h[51:32]) to a
non-zero value initiates the FID_Change protocol.
– The new VID[4:0] code that will be driven to the
– The new FID[4:0] code that will be used by the
– A Stop Grant Timeout Count (SGTC[19:0], MSR
DC/DC converter from the SOFTVID[4:0] outputs
of the processor that selects the new core voltage
level.
processor to dictate its new operating frequency.
C001_0041h[51:32]) value that determines how
many SYSCLK/SYSCLK# 133 MHz clock periods
the processor will remain in the FID_Change
state. This time accounts for the time that it takes
for the PLL of the processor to lock to the new
core frequency and the time that it takes for the
core voltage of the processor to ramp to the new
value.
FID_Change Protocol Example
of
the
processor
31177H
is
transitioned.
Two
In response to receiving the FID_Change special cycle, the
Northbridge is required to disconnect. The Northbridge
completes any in-progress bus cycles and then disable its
arbiter before disconnecting the AMD processor system
bus so that it will not initiate a AMD processor system bus
connect based on bus master or other activity. The North-
bridge must disconnect the AMD processor system bus or
the system will hang because the processor is not execut-
ing any operating system or application code and is waiting
for the AMD processor system bus to disconnect so that it
can continue with the FID_Change protocol. The North-
bridge initiates an AMD processor system bus disconnect
in the usual manner; it de-asserts CONNECT.
The processor allows the disconnect to complete by de-
asserting PROCRDY. The Northbridge completes the dis-
connect by asserting CLKFWDRST.
Once the AMD processor system bus has been discon-
nected in response to a FID_Change special cycle, the
Northbridge is not allowed to initiate a re-connect, the pro-
cessor is responsible for the eventual re-connect.
After the AMD processor system bus is disconnected, the
processor enters a low-power state where the clock grid is
ramped down by a value specified in the CLK_CTL MSR
(MSR C001_001Bh).
After entering the low-power state, the processor will:
• Begin counting down the value that was programmed
• Drive the new VID[4:0] value on SOFTVID[4:0], causing
• Drive the new FID[4:0] value to its PLL, causing the PLL
When the SGTC count reaches zero, the processor ramps
its entire clock grid to full frequency (the PLL is already
locked to) and signal that it is ready for the Northbridge to
transmit the new SIP (Serial Initialization Packet) stream
associated with the new processor core operating fre-
quency. The processor signals this by pulsing PROCRDY
high and then low.
The Northbridge responds to this high pulse on PROCRDY
by pulsing CLKFWDRST low and then transferring a SIP
stream as it does after PROCRDY is de-asserted after the
de-assertion of RESET#. The difference is that the SIP
stream that the Northbridge transmits to the processor now
corresponds to the FID[4:0] that was transmitted on
SDATA[36:32] during the FID_Change special cycle.
After the SIP stream is transmitted, the processor initiates
the AMD processor system bus connect sequence by
asserting PROCRDY. The Northbridge responds by de-
asserting CLKFWDRST. The forward clocks are started
and the processor issues a Connect special cycle.
into the SGTC field.
its core voltage to transition.
to lock to the new core frequency.
AMD Geode™ NX Processors Data Book
Power Management