ANXL1500FGC3M AMD (ADVANCED MICRO DEVICES), ANXL1500FGC3M Datasheet - Page 34

• Manufacturer Part Number: ANXL1500FGC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXL1500FGC3M

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.1.1
The Working state is the state in which the processor is
executing instructions.
3.1.2
When the processor executes the HLT instruction, the pro-
cessor enters the Halt state and issues a Halt special cycle
to the AMD processor system bus. The processor only
enters the low power state dictated by the CLK_Ctl MSR
(MSR C001_001Bh) if the system controller (Northbridge)
disconnects the AMD processor system bus in response to
the Halt special cycle.
If STPCLK# is asserted, the processor exits the Halt state
and enters the Stop Grant state. The processor initiates a
system bus connect, if it is disconnected, then issues a
Stop Grant special cycle. When STPCLK# is de-asserted,
the processor exits the Stop Grant state and re-enters the
Halt state. The processor issues a Halt special cycle when
reentering the Halt state.
The Halt state is exited when the processor detects the
assertion of INIT#, INTR, NMI, RESET#, or SMI#, or via a
local APIC interrupt message. When the Halt state is exited
the processor initiates an AMD processor system bus con-
nect if it is disconnected.
3.1.3
The processor enters the Stop Grant state upon recogni-
tion of assertion of the STPCLK# input. After entering the
Stop Grant state, the processor issues a Stop Grant spe-
cial bus cycle on the AMD processor system bus. The pro-
cessor is not in a low-power state at this time, because the
AMD processor system bus is still connected. After the
Northbridge disconnects the AMD processor system bus in
response to the Stop Grant special bus cycle, the proces-
sor enters a low-power state dictated by the CLK_Ctl MSR
(MSR C001_001Bh). If the Northbridge needs to probe the
processor during the Stop Grant state while the system bus
is disconnected, it must first connect the system bus. Con-
necting the system bus places the processor into the
higher power probe state. After the Northbridge has com-
pleted all probes of the processor, the Northbridge must
disconnect the AMD processor system bus again so that
the processor can return to the low-power state. During the
Stop Grant states, the processor latches INIT#, INTR, NMI,
SMI#, or a local APIC interrupt message if they are
asserted.
The Stop Grant state is exited upon the de-assertion of
STPCLK# or the assertion of RESET#. When STPCLK# is
de-asserted, the processor initiates a connect of the
AMD processor system bus if it is disconnected. After the
processor enters the Working state, any pending interrupts
are recognized and serviced and the processor resumes
execution at the instruction boundary where STPCLK# was
initially recognized. If RESET# is sampled asserted during
the Stop Grant state, the processor exits the Stop Grant
state and the reset process begins.
34
Working State
Halt State
Stop Grant States
31177H
There are two mechanisms for asserting STPCLK#: hard-
ware and software.
The Southbridge can force STPCLK# assertion for throt-
tling to protect the processor from exceeding its maximum
case temperature. Typically this is accomplished by assert-
ing the THERM# input to the Southbridge. Throttling
asserts STPCLK# for a percentage of a predefined throt-
tling period: STPCLK# is repetitively asserted and de-
asserted until THERM# is de-asserted.
Software can force the processor into the Stop Grant state
by accessing ACPI-defined registers typically located in the
Southbridge.
The operating system places the processor into the C2
Stop Grant state by reading the P_LVL2 register in the
Southbridge.
If an ACPI Thermal Zone is defined for the processor, the
operating system can initiate throttling with STPCLK#
using the ACPI defined P_CNT register in the Southbridge.
The Northbridge connects the AMD processor system bus,
and the processor enters the Probe state to service cache
snoops during Stop Grant for C2 or throttling.
In C2, probes are allowed, as shown in Figure 3-1 on page
33.
• If an ACPI Thermal Zone is defined for the processor,
• The operating system places the processor into the C3
• The Stop Grant state is also entered for the S1,
the operating system can initiate throttling with
STPCLK# using the ACPI defined P_CNT register in the
Southbridge. The Northbridge connects the
AMD processor system bus, and the processor enters
the Probe state to service cache snoops during Stop
Grant for C2 or throttling.
Stop Grant state by reading the P_LVL3 register in the
Southbridge. In C3, the operating system and North-
bridge hardware enforce a policy that prevents the
processor from being probed. The Southbridge de-
asserts STPCLK# and brings the processor out of the
C3 Stop Grant state if a bus master request, interrupt, or
any other enabled resume event occurs.
Powered On Suspend, system sleep state based on a
write to the SLP_TYP and SLP_EN fields in the
ACPI-defined Power Management 1 control register in
the Southbridge. During the S1 sleep state, system soft-
ware ensures no bus master or probe activity occurs.
The Southbridge de-asserts STPCLK# and brings the
processor out of the S1 Stop Grant state when any
enabled resume event occurs.
AMD Geode™ NX Processors Data Book
Power Management