ANXL1500FGC3M AMD (ADVANCED MICRO DEVICES), ANXL1500FGC3M Datasheet - Page 14

• Manufacturer Part Number: ANXL1500FGC3M
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ANXL1500FGC3M

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.1
The architecture is designed to deliver excellent data
movement bandwidth for next-generation x86 platforms as
well as the high-performance required by enterprise-class
application software. The system bus architecture consists
of three high-speed channels (a unidirectional processor
request channel, a unidirectional probe channel, and a 64-
bit bidirectional data channel), source-synchronous clock-
ing, and a packet-based protocol. In addition, the system
bus supports several control, clock, and legacy signals.
The interface signals use an impedance controlled
push-pull, low-voltage, swing-signaling technology con-
tained within the Socket A socket.
For more information, see Section 2.1.3 "AMD Processor
System Bus Signals", Section 2.3.4 "AMD Processor Sys-
tem Bus Interface Signals" on page 26, and the
AMD Athlon™ Processor System Bus Specification (publi-
cation ID 21902).
2.1.1
The AMD processor system bus uses a low-voltage, swing-
signaling technology, that has been enhanced to provide
larger noise margins, reduced ringing, and variable voltage
levels. The signals are push-pull and impedance compen-
sated. The signal inputs use differential receivers that
require a reference voltage (V
used by the receivers to determine if a signal is asserted or
de-asserted by the source. Termination resistors are not
needed because the driver is impedance-matched to the
circuit board and a high impedance reflection is used at the
receiver to bring the signal past the input threshold.
For more information about signals, see Section 2.3 "Sig-
nal Descriptions" on page 25.
2.1.2
The AMD Geode NX processors support push-pull (PP)
drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1 = PP). The
impedance of the PP drivers is set to match the impedance
of the circuit board by two external resistors connected to
the ZN and ZP pins.
See Section 2.3.12 "Power, Ground and Compensation
Circuit Connections" on page 31 for more information.
14
Interface Signals Architecture
Signaling Technology
Push-Pull (PP) Drivers
31177H
REF
). The reference signal is
2.1.3
The AMD processor system bus is a clock-forwarded,
point-to-point
point-to-point channels:
• A 13-bit unidirectional output address/command channel
• A 13-bit unidirectional input address/command channel
• A 72-bit bidirectional data channel
For more information, see Section 5.0 "Electrical Specifica-
tions" on page 47 and the AMD Athlon™ Processor Sys-
tem Bus Specification (publication ID 21902).
2.2
This subsection defines the pin assignments:
• Figure 2-2 on page 15 and Figure 2-3 on page 16 shows
• Table 2-1 on page 17 lists all the pins sorted by pin
• Table 2-2 on page 23 is a quick reference and sorts the
PGA Orientation Pins
No pin is present at pin locations A1 and AN1. Circuit
board designers should not allow for a PGA socket pin at
these locations.
For more information, see the AMD Athlon™ Processor-
Based Motherboard Design Guide (publication ID 24363)
and AMD Geode™ NX Processors Addendum to
AMD Athlon™
Guide (publication ID 31860).
the Organic Pin Grid Array (OPGA) for the Geode NX
processor, top and bottom views respectively. Because
some of the pin names are too long to fit in the grid, they
are abbreviated.
number along with the abbreviation (where necessary)
and some additional pin information.
pins alphabetically by signal name (full name; no abbre-
viation or other parameters are called out) with the
corresponding pin number.
AMD Processor System Bus Signals
Pin Assignments
interface
Processor-Based
AMD Geode™ NX Processors Data Book
with
the
Motherboard
following
Signal Definitions
Design
three