PIC16LF1847-E/MV Microchip Technology, PIC16LF1847-E/MV Datasheet - Page 266
![14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan](/photos/16/12/161255/qfn28_sml.jpg)
PIC16LF1847-E/MV
Manufacturer Part Number
PIC16LF1847-E/MV
Description
14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ mTouch™ 16Fr
Datasheet
1.PIC16F1847-EP.pdf
(408 pages)
Specifications of PIC16LF1847-E/MV
Processor Series
PIC16LF
Core
RISC
Data Bus Width
10 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
1024 B
Interface Type
SPI, I2C
Maximum Clock Frequency
32 KHZ
Number Of Programmable I/os
15
Number Of Timers
3
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UQFN-28
Operating Temperature Range
- 40 C to + 125 C
Processor To Be Evaluated
PIC16F1847
Supply Current (max)
34 uA
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
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PIC16(L)F1847
25.6.4 I
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPxCON2 register. If the
SDAx and SCLx pins are sampled high, the Baud Rate
Generator
SSPxADD<7:0> and starts its count. If SCLx and
SDAx are both sampled high when the Baud Rate
Generator times out (T
low. The action of the SDAx being driven low while
SCLx is high is the Start condition and causes the S bit
of the SSPxSTAT1 register to be set. Following this,
the Baud Rate Generator is reloaded with the contents
of SSPxADD<7:0> and resumes its count. When the
Baud Rate Generator times out (T
the SSPxCON2 register will be automatically cleared
FIGURE 25-26:
DS41453B-page 266
CONDITION TIMING
2
C MASTER MODE START
is
reloaded
FIRST START BIT TIMING
Write to SEN bit occurs here
BRG
), the SDAx pin is driven
with
SDAx
SCLx
BRG
the
), the SEN bit of
contents
SDAx = 1,
SCLx = 1
T
BRG
Preliminary
of
S
Set S bit (SSPxSTAT<3>)
T
BRG
At completion of Start bit,
hardware clears SEN bit
by hardware; the Baud Rate Generator is suspended,
leaving the SDAx line held low and the Start condition
is complete.
and sets SSPxIF bit
Note 1: If at the beginning of the Start condition,
Write to SSPxBUF occurs here
T
BRG
2: The Philips I
1st bit
the SDAx and SCLx pins are already sam-
pled low, or if during the Start condition,
the SCLx line is sampled low before the
SDAx line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLxIF, is set, the Start condition is
aborted and the I
its Idle state.
bus collision cannot occur on a Start.
T
BRG
2011 Microchip Technology Inc.
2
C Specification states that a
2nd bit
2
C module is reset into
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