MAX11043ATL+ Maxim Integrated Products, MAX11043ATL+ Datasheet - Page 25

• Manufacturer Part Number: MAX11043ATL+
• Description: IC ADC 16BIT W/DAC 40-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX11043ATL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 9.6M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 4
• Conversion Rate: 1600 KSPs
• Resolution: 16 bit
• Interface Type: SPI
• Voltage Reference: 2.5 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 2963 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write allowed only if flash busy bit is zero.
This is a 16-bit register that contains the data for a flash
write operation. Default = 0.
This is a read-only register. Data is valid only if flash
busy is zero.
This is a 16-bit register that contains the data for a flash
read operation.
The flash memory consists of 2048 words by 16 bits. The
3 MSBs of the flash address select one of eight pages of
256 words each. Page zero contains the default filter
coefficients for channels A and B. Page one contains the
default filter coefficients for channels C and D. Use
pages two and three for the coefficients of custom filters.
When the first word on page two contains a nonzero
value, the MAX11043 loads these pages into C-RAM at
power-up instead of the default values from pages zero
and one. Flash pages zero and one include trim data.
Unique trim data optimizes the performance of each
MAX11043. Coefficients for the stage 1 filters and ADC
gain are individually programmed at the factory to com-
Table 3. Stage 1 Filter Selection
Table 4. C-RAM and Flash Memory Map for Channel A Flash Page One*
* For channel B add 80h, for channel C add 100h, and for channel D add 180h. To write to pages two and three of flash, add 200h to
these values.
EQ filter stage 1 (C-RAM address 03h–05h)
LP filter for ADC gain of 1, 2, and 4; stage 1 (C-RAM address 1Dh–1Fh)
LP filter for ADC gain of 8; stage 1 (C-RAM address 3Dh–3Fh)
LP filter for ADC gain of 16; stage 1 (C-RAM address 23h–25h)
ADDRESS
C-RAM
00h
01h
02h
03h
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
ADDRESS
Flash and C-RAM Register Map
FLASH
STAGE 1 COEFFICIENT ADDRESS
01h*
06h*
07h*
00h
02h
03h
04h
05h
______________________________________________________________________________________
Flash Data Out Register (1Bh)
Flash Data In Register (1Ah)
EQ gain trim for gain = 1
User trim for EQ gain, default = 2000h
Not used
EQ filter coefficient -A2 for filter stage 1
MSB FOR C-RAM
—
—
—
—
pensate for manufacturing variations in the analog por-
tion of the IC. These coefficients vary depending on the
PGA gain setting and if the analog equalizer is used. To
allow for these different modes, several sets of stage 1
coefficients are stored in flash. Bits in the CONGIF reg-
ister select which set of stage 1 coefficients are used.
Table 3 shows the C-RAM addresses used for each
CONFIG setting. To maintain optimum performance
when using custom filters, copy the trim data from flash
pages zero and one to the corresponding locations in
flash pages two and three or to C-RAM when writing
directly to C-RAM.
For custom filters, use stages 2–7 first, and only change
the stage 1 coefficients when all seven stages require
customization.
To load the coefficients directly to C-RAM, create a 32-
bit data word by concatenating the data in adjacent
flash locations as shown in Table 3. The C-RAM
addresses below are for channel A; for channel B add
40h, for channel C add 80h, and for channel D add C0h.
Multiple addresses exist for some stage 1 filter coeffi-
cients as shown in Table 4. The address accessed by
the filter depends on the configuration bits as shown in
Table 3.
Not used
Not used
Not used
EQ filter gain for filter stage 1
EQ
X
1
0
0
PDPGA
LSB FOR C-RAM
0
1
0
0
—
—
—
—
MODG
XX
XX
00
XX
PGAG
X
X
0
1
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