MAX11043ATL+ Maxim Integrated Products, MAX11043ATL+ Datasheet

IC ADC 16BIT W/DAC 40-TQFN-EP

MAX11043ATL+

Manufacturer Part Number
MAX11043ATL+
Description
IC ADC 16BIT W/DAC 40-TQFN-EP
Manufacturer
Maxim Integrated Products
Type
ADC, DACr
Datasheet

Specifications of MAX11043ATL+

Resolution (bits)
16 b
Sampling Rate (per Second)
9.6M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
40-TQFN Exposed Pad
Number Of Converters
4
Conversion Rate
1600 KSPs
Resolution
16 bit
Interface Type
SPI
Voltage Reference
2.5 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Power Dissipation
2963 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Input Voltage
3.3 V
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX11043 features 4 single-ended or differential
channels of simultaneous-sampling ADCs with 16-bit
resolution. The MAX11043 contains a versatile filter
block and programmable-gain amplifier (PGA) per
channel. The filter consists of seven cascaded 2nd-
order filter sections for each channel, allowing the con-
struction of a 14th-order filter. The filter coefficients are
user-programmable. Configure each 2nd-order filter as
lowpass (LP), highpass (HP), or bandpass (BP) with
optional rectification. Gain and phase mismatch of the
analog signal path is better than -50dB.
The ADC can digitize signals up to 200kHz. A 40MHz
serial interface provides communication to and from the
device. The SPI™ interface provides throughput of
1600ksps; 4 channels at 400ksps per channel or 2
channels at 800ksps per channel. A software-selec-
table scan mode allows reading the ADC results while
simultaneously updating the DAC. Other features of the
MAX11043 include an internal (+2.5V) or external
(+2.0V to +2.8V) reference, power-saving modes, and
a PGA with gains of 1 to 64. The PGA includes an
equalizer (EQ) function that automatically boosts low-
amplitude, high-frequency signals for applications such
as CW-chirp radar.
The MAX11043 includes two 8-bit coarse DACs that set
the high and low references for a second-stage 12-bit
fine DAC, typically used for VCO control. Use software
controls to write to the DAC or step the DAC up and
down under hardware control in programmable steps.
The device operates from a +3.0V to +3.6V supply. The
MAX11043 is available in a 40-pin, 6mm x 6mm TQFN
package and operates over the extended -40°C to
+125°C temperature range.
19-4250; Rev 1; 3/10
SPI is a trademark of Motorola, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
Automotive Radar Systems
Data Acquisition Systems
Industrial Controls
Power-Grid Monitoring
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
________________________________________________________________ Maxim Integrated Products
General Description
Applications
o 4 Single-Ended or Differential Channels of
o ±10 LSB INL, ±1 LSB DNL, No Missing Codes
o 93dB SFDR at 100kHz Input
o PGA with Gain of 1, 2, 4, 8, 16, 32, or 64 for
o EQ Function Automatically Boosts
o Seven-Stage Internal Programmable Biquad
o High Throughput, 400ksps per Channel for 4
o Dual-Stage DAC
o +2.5V Internal Reference or +2.0V to +2.8V
o Single +3.3V Operation
o Shutdown and Power-Saving Modes
o 40-Pin, 6mm x 6mm TQFN Package
o -40°C to +125°C Operating Temperature
+ Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
* EP = Exposed pad.
** Future product—contact factory for availability.
MAX11043ATL+
MAX11043ATL/V+**
Simultaneous-Sampling, 16-Bit ADCs
Each Channel
High-Frequency, Low-Amplitude Signals
Filters per Channel
Channels
External Reference
TOP VIEW
*CONNECT EP TO AGND.
Two 8-Bit Coarse Reference DACs
12-Bit Fine DAC
PART
AINDN
REFBP
AINCN
AINDP
AINCP
AINBP
AGND
REFC
REFB
I.C.
31
32
33
34
35
36
37
38
39
40
30
1
29
2
+
28
3
Ordering Information
-40°C to +125°C
-40°C to +125°C
TEMP RANGE
27
4
MAX11043
TQFN
26
5
Pin Configuration
25
6
24 23 22
7
*EP
8
9
10
21
PIN-PACKAGE
Features
20 OSCOUT
19
18
17
16
15
14
13
12
11
40 TQFN-EP*
40 TQFN-EP*
OSCIN
EOC
I.C.
SCLK
DIN
DOUT
CS
CONVRUN
DACSTEP
1

Related parts for MAX11043ATL+

MAX11043ATL+ Summary of contents

Page 1

... External Reference o Single +3.3V Operation o Shutdown and Power-Saving Modes o 40-Pin, 6mm x 6mm TQFN Package o -40°C to +125°C Operating Temperature PART MAX11043ATL+ MAX11043ATL/V+** + Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part Exposed pad. ** Future product—contact factory for availability. TOP VIEW ...

Page 2

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ABSOLUTE MAXIMUM RATINGS AVDD to AGND ....................................................-0.3V to +4.0V DVDD to DGND .....................................................-0.3V to +4.0V DVREG to DGND...................................................-0.3V to +3.0V AGND to DGND.....................................................-0.3V to +0.3V Analog I/O, REFDACH, REFDACL, ...

Page 3

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V +3.0V, C AVDD DVDD +2.5V (external reference), V REFA REFB REFC ...

Page 4

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V +3.0V, C AVDD DVDD +2.5V (external reference), V REFA REFB REFC ...

Page 5

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V +3.0V, C AVDD DVDD +2.5V (external reference), V REFA REFB REFC ...

Page 6

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V +3.0V, C AVDD DVDD +2.5V (external reference), V REFA REFB REFC ...

Page 7

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V +3.0V, C AVDD DVDD +2.5V (external reference), V REFA REFB REFC ...

Page 8

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC (V = +3.3V +3.0V, f AVDD DVDD SCLK T = +25°C, unless otherwise noted.) A 400ksps FFT EQ MODE 5kHz 560mV ...

Page 9

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC (V = +3.3V +3.0V, f AVDD DVDD SCLK T = +25°C, unless otherwise noted.) A FINE DAC SETTLING 1% STEP-DOWN MAX11043 toc12 20mV/div 1200mV 1μs/div COARSE DAC ...

Page 10

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC PIN NAME 1 AINBN Channel B Analog Negative Input 2 REFA Channel A Reference Bypass. Bypass REFA with a nominal 1µF capacitor to AGND. 3 AINAN Channel A Analog ...

Page 11

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC AINAP PGA EQ AINAN REFA AINBP PGA EQ AINBN REFB AINCP PGA EQ AINCN REFC AINDP PGA EQ AINDN REFD R +2.5V VOLTAGE R REFERENCE REFBP ______________________________________________________________________________________ SIGMA-DELTA PROGRAMMABLE ...

Page 12

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Detailed Description The MAX11043 features 4 single-ended or differential channels of simultaneous-sampling ADCs with 16-bit resolution. The MAX11043 contains a versatile filter block and PGA per channel. The filter ...

Page 13

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC modulator running at 9.6Msps. Operating the modulator at a lower sample rate causes a proportional reduction in the frequency response of the sinc 5 filter. The total attenuation of ...

Page 14

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Filter coefficients A1 and B1 are always limited to -1, 0, and 1. Filter coefficients A2, A3, and B2 are stored as 16-bit two’s complement values ...

Page 15

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Programmable Gain Amplifier Each ADC channel features an input buffer with input impedance of at least 5kΩ and programmable gain of eight or 16. When set to a gain ...

Page 16

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Reference (REFBP) The MAX11043 features an internal 2.5V bandgap ref- erence. Bypass REFBP with a 1µF capacitor or power down the buffer amplifier and drive REFBP with an external ...

Page 17

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC CSS SCLK START ADR 3 ADR 2 DIN ADR 4 X HIGH IMPEDANCE DOUT Figure 9. SPI 8-Bit Write Operation t ...

Page 18

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 2. SPI Register Map ADDRESS REGISTER NAME 00h ADCA 01h ADCB 02h ADCC 03h ADCD 04h ADCAB 05h ADCCD 06h ADCABCD 07h Status 08h Configuration 09h DAC 0Ah ...

Page 19

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Register Functions ADCA, ADCB, ADCC, and ADCD Result Registers (00h–03h) The ADC channel and D result registers pro- vide the result data from the 4 ADC ...

Page 20

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC SCHAN_<4:1>: Automatic ADC result output for each channel ( and D ADC channel data is output on DOUT each time a new result is valid ...

Page 21

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC CONFIG_ Register (0Ch–0Fh) BIT 15 BIT 14 BIT BIT 7 BIT 6 BIT 5 EQ MODG1 MODG0 This register sets the input gain of each ADC ...

Page 22

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Reference Register (10h) BIT 15 BIT 14 BIT BIT 7 BIT 6 BIT 5 EXTREF EXBUFA EXBUFB Reserved<15:13>: Reserved. Set to 0. PURGE4:PURGE0<12:8>: Filter purge interval. ...

Page 23

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Fine Gain A/B/C/D Registers (11h–14h) Fine gain for each channel is a two’s complement binary value (8192 x desired gain). FINE GAIN REGISTER 7FFFh 4000h 2001h 2000h 1FFFh 1000h ...

Page 24

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Flash Mode Register (18h) BIT 7 BIT 6 BIT 5 FM2 FM1 (Flashmode2) (Flashmode1) (Flashmode0) Write allowed only if flash busy bit is zero. FM2:FM0<7:5>: Flash operation (default 0). ...

Page 25

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Flash Data In Register (1Ah) Write allowed only if flash busy bit is zero. This is a 16-bit register that contains the data for a flash write operation. Default ...

Page 26

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM FLASH ADDRESS ADDRESS 08h 04h 09h* EQ filter coefficient -A3 for filter stage 1 0Ah* 05h 0Bh* EQ filter coefficient ...

Page 27

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM FLASH ADDRESS ADDRESS 2Eh 17h 2Fh EQ filter coefficient B2 for filter stage 7 30h 18h 31h* ADC gain trim ...

Page 28

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM FLASH ADDRESS ADDRESS 4Eh 27h 4Fh LP filter coefficient -A3 for filter stage 2 50h 28h 51h LP filter coefficient ...

Page 29

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 4. C-RAM and Flash Memory Map (continued) C-RAM FLASH ADDRESS ADDRESS 76h 3Bh 77h* ADC gain trim for gain = 32 78h 3Ch 79h* ADC gain trim for ...

Page 30

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC Table 5. Typical Filter Coefficients Register Map (LP Filter Channel A, Stage 3) COEFFICIENT FLASH ADDRESS 52h 53h 54h 55h 56h 57h Format for Filter Stage Gain (52h) BIT ...

Page 31

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC A2, A3, and B2 Filter Coefficient Format (52h, 54h, 56h) Filter coefficients A2, A3, and B2 are stored as 16-bit two’s complement values in the - ...

Page 32

Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC *SEE NOTE RADAR FRONT END *SEE NOTE *SEE NOTE *SEE NOTE *NOTE: CONNECT TO AGND FOR SINGLE-ENDED OPERATION. 32 ______________________________________________________________________________________ ECHO+ AINAP AINAN ECHO- REFA ECHO+ AINBP AINBN ECHO- ...

Page 33

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 © 2010 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc ...

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