AD9271BSVZRL-25 Analog Devices Inc, AD9271BSVZRL-25 Datasheet - Page 39

• Manufacturer Part Number: AD9271BSVZRL-25
• Description: IC ADC OCT 12BIT 25MSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9271BSVZRL-25

• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 1.06W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Power Dissipation Pd: 150mW
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage: 1.8V
• Sample Rate: 25 MSPS
• Termination Type: SMD
• Supply Voltage Max: 1.9V
• Input Channels Per Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Addr.
(Hex)
0D
0F
10
11
14
15
16
Register Name
test_io
flex_channel_input
flex_offset
flex_gain
output_mode
output_adjust
output_phase
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Filter cutoff frequency control
0000 = 1.3 × 1/3 × f
0001 = 1.2 × 1/3 × f
0010 = 1.1 × 1/3 × f
0011 = 1.0 × 1/3 × f
0100 = 0.9 × 1/3 × f
0101 = 0.8 × 1/3 × f
0110 = 0.7 × 1/3 × f
X
X
X
X
X
Bit 7
(MSB)
Bit 6
X
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X
X
X
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
Bit 5
Reset PN
long gen
1 = on
0 = off
(default)
6-bit LNA offset adjustment
011001 = 50 MSPS speed grade
011010 = 40 MSPS speed grade
011111 = 25 MSPS speed grade
X
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
Rev. B | Page 39 of 60
Bit 4
Reset PN
short
gen
1 = on
0 = off
(default)
X
X
X
Bit 3
Output test mode—see
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by output_mode)
X
X
X
X
0011 = output clock phase adjust
(0000 through 1010)
(Default: 180° relative to data edge)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge
0100 = 240° relative to data edge
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = 420° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
Bit 2
X
X
Output
invert
1 = on
0 = off
(default)
X
Bit 1
Table 10
X
LNA gain
00 = 5×
01 = 6×
10 = 8×
00 = offset binary
(default)
01 = twos
complement
X
Bit 0
(LSB)
DCO±
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
X
Default
Value
0x00
0x30
0x20
0x01
0x00
0x00
0x03
Notes/
Comments
When this
register is set,
the test data is
placed on the
output pins in
place of normal
data. (Local,
expect for
PN sequence.)
Antialiasing
filter cutoff
(global).
LNA force
offset
correction
(local).
LNA gain
adjustment
(global).
Configures the
outputs and
the format of
the data.
Determines
LVDS or other
output prop
erties. Primarily
functions to set
the LVDS span
and common-
mode levels in
place of an
external
resistor.
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used
to supply the
output clock.
Internal
latching
is unaffected.
AD9271