AD9271BSVZRL-25 Analog Devices Inc, AD9271BSVZRL-25 Datasheet - Page 25

• Manufacturer Part Number: AD9271BSVZRL-25
• Description: IC ADC OCT 12BIT 25MSPS 100-TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9271BSVZRL-25

• Number Of Bits: 12
• Sampling Rate (per Second): 25M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 1.06W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Power Dissipation Pd: 150mW
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage: 1.8V
• Sample Rate: 25 MSPS
• Termination Type: SMD
• Supply Voltage Max: 1.9V
• Input Channels Per Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9271-50EBZ - BOARD EVALUATION AD9271 50MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Crosspoint Switch
Each LNA is followed by a transconductance amp for V/I con-
version. Currents can be routed to one of six pairs of differential
outputs or to 12 single-ended outputs for summing. Each CWD
output pin sinks 2.4 mA dc current, and the signal has a full-scale
current of ±2 mA for each channel selected by the crosspoint
switch. For example, if four channels were to be summed on
one CWD output, the output would sink 9.6 mA dc and have a
full-scale current output of ±8 mA. The maximum number of
channels combined must be considered when setting the load
impedance for I/V conversion to ensure that the full-scale swing
and common-mode voltage are within the operating limits of
the AD9271. When interfacing to the AD8339, a common-
mode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are
desired. This can be accomplished by connecting an inductor
between each CWD output and a 2.5 V supply, and then
connecting either a single-ended or differential load resistance
to the CWD± outputs. The value of resistance should be
calculated based on the maximum number of channels that can
be combined.
CWD± outputs are required under full-scale swing to be greater
than 1.5 V and less than CWVDD (3.3 V supply).
TGC OPERATION
The TGC signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion; however, the LNAs
are designed to be driven from a single-ended signal source. Gain
values are referenced from the single-ended LNA input to the
differential ADC input. A simple exercise in understanding the
maximum and minimum gain requirements is shown in Figure 48.
(5.4µV rms) @ AAF BW = 15MHz
In summary, the maximum gain required is determined by
The minimum gain required is determined by
Therefore, a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth
should suffice in achieving the dynamic range required for most
of today’s ultrasound systems.
LNA + VGA NOISE = 1.4nV/ Hz
(ADC Noise Floor/VGA Input Noise Floor) + Margin =
(ADC Input FS/VGA Input FS) + Margin =
Figure 48. Gain Requirements of TGC for a 12-Bit, 40 MSPS ADC
LNA INPUT-REFERRED
20 log(224/5.4) + 8 dB = 40.3 dB
20 log(2/0.333) – 5 dB = 10.6 dB
(0.333V p-p SE)
NOISE FLOOR
LNA
MINIMUM GAIN
LNA FS
87dB
VGA GAIN RANGE > 30dB
MAX CHANNEL GAIN > 40dB
MAXIMUM GAIN
70dB
>8dB MARGIN
ADC NOISE FLOOR
(224µV rms)
ADC FS (2V p-p)
~5dB MARGIN
ADC
Rev. B | Page 25 of 60
The system gain is distributed as listed in Table 8.
Table 8. Channel Gain Distribution
Section
LNA
Attenuator
VGA Amp
Filter
ADC
Total
The linear-in-dB gain (law conformance) range of the TGC path
is 30 dB, extending from 10 dB to 40 dB. The slope of the gain
control interface is 31.6 dB/V, and the gain control range is 0 V
to 1 V as specified in Equation 3. Equation 4 is the expression
for channel gain.
where ICPT is the intercept point of the TGC gain.
In its default condition, the LNA has a gain of 15.6 dB (6×) and
the VGA gain is −6 dB if the voltage on the GAIN± pins is 0 V.
This gives rise to a total gain (or ICPT) of 10 dB through the
TGC path if the LNA input is unmatched, or of 4 dB if the LNA
is matched to 50 Ω (R
pins is 1 V, however, the VGA gain is 24 dB. This gives rise to a
total gain of 40 dB through the TGC path if the LNA input is
unmatched, or of 34 dB if the LNA input is matched.
Each LNA output is dc-coupled to a VGA input. The VGA consists
of an attenuator with a range of 30 dB followed by an amplifier
with 24 dB of gain for a net gain range of −6 dB to +24 dB. The
X-AMP gain-interpolation technique results in low gain error
and uniform bandwidth, and differential signal paths minimize
distortion.
At low gains, the VGA should limit the system noise perfor-
mance (SNR); at high gains, the noise is defined by the source and
LNA. The maximum voltage swing is bound by the full-scale
peak-to-peak ADC input voltage (2 V p-p).
Both the LNA and VGA have limitations within each section of
the TGC path, depending on the voltage applied to the GAIN+ and
GAIN− pins. The LNA has three limitations, or full-scale settings,
depending on the gain selection applied through the SPI interface.
When a voltage of 0.2 V or less is applied to the GAIN± pins, the
LNA operates near the full-scale input range to maximize the
dynamic range of the ADC without clipping the signal. When
more than 0.2 V is applied to the GAIN± pins, the input signal to
the LNA must be lowered to keep it within the full-scale range
of the ADC (see Figure 49).
V
Gain
GAIN
(
(
dB
V
)
)
=
=
(
31
GAIN
6 .
dB
V
+
)
V
FB
−
GAIN
= 200 Ω). If the voltage on the GAIN±
(
GAIN
Nominal Gain (dB)
14/15.6/18
0 to −30
24
0
0
8.4 to 38.4/10 to 40/12.4 to 42.4
+
ICPT
−
)
+
0
5 .
AD9271
(3)
(4)