AD9271 Analog Devices, AD9271 Datasheet
AD9271
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AD9271 Summary of contents
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... Medical imaging/ultrasound Automotive radar GENERAL DESCRIPTION The AD9271 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amp- lifier (VGA) with low noise preamplifier (LNA); an antialiasing filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC) ...
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... AD9271 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 8 ADC Timing Diagrams ............................................................... 9 Absolute Maximum Ratings .......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 14 Typical Performance Characteristics ........................................... 16 Theory of Operation ...
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... Fabricated in an advanced CMOS process, the AD9271 is available × 16 mm, RoHS compliant, 100-lead TQFP specified over the industrial temperature range of − ...
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... DC/350/700 1/3 × f 1/3 × f SAMPLE ( 18) ±15 ±15 ±2 ±2 1.7/1.6/1.5 1.6/1.4/1.3 −30 −30 −50 +50 −35 65.8 64.4 62 59.7 Rev Page MHz Ω, LNA gain = 15.6 dB (6), AAF S AD9271-50 Max Min Typ Max 14/15.6/18 8/9.6/12 400/333/250 1.4 50 100 1.1 1.3/1.2/1.1 770/650/495 6.7 4.2 DC/350/700 1/3 × f SAMPLE SAMPLE (8 to 18) ±15 ± ...
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... Rev Page AD9271 AD9271-50 Max Min Typ Max Unit −71 dBFS −68 dBFS −74 dBFS −66 dBFS −68.5 dBc −70 dB − Degrees +0.8 dB +1.2 −1.2 +1.2 dB −1.2 dB +1.3 −1.3 +1 ...
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... Typ Max Min Typ 1.7 1.8 1.9 1.7 1.8 1.7 1.8 1.9 1.7 1.8 3.0 3.3 3.6 3.0 3.3 505 613 136 160 46.7 48.7 993 1063 1190 192 216 4.5 101 ± Rev Page AD9271-50 Max Min Typ Max Unit 1.9 1.7 1.8 1.9 V 1.9 1.7 1.8 1.9 V 3.6 3.0 3.3 3.6 742 mA 170 1280 1425 1494 mW 224 mW 4.5 4.5 mW 112.5 120 mV/V 12 Bits ± ...
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... Full 1.2 Full 25°C 25°C Full 1.2 Full 25°C 25°C Full 1.2 Full 0 25°C 25°C Full Full Full 247 Full 1.125 1 Full 150 Full 1.10 Rev Page AD9271 Typ Max Unit CMOS/LVDS/LVPECL mV p-p 1 kΩ 1.5 pF 3 kΩ 0.5 pF 3 kΩ 0.5 pF DRVDD + 0 ...
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... AD9271 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 mV p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter 2 CLOCK Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High ( Clock Pulse Width Low ( OUTPUT PARAMETERS ...
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... – – – – – – – 9 Figure 3. 12-Bit Data Serial Stream, LSB First Rev Page AD9271 MSB D10 N – – – – – – ...
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... AD9271 ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect To ELECTRICAL AVDD GND DRVDD GND CWVDD GND GND GND AVDD DRVDD Digital Outputs GND (DOUTx+, DOUTx−, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− GND LI-x LG-x LO-x LG-x LOSW-x LG-x CWDx−, CWDx+ GND SDIO, GAIN+, GAIN− ...
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... LNA Analog Input for Channel F LNA Ground for Channel F LNA Analog Output for Channel G LNA Analog Output Complement for Channel G LNA Analog Input for Channel G LNA Ground for Channel G LNA Analog Output for Channel H Rev Page AD9271 LI-D 75 LG-D 74 AVDD 73 AVDD ...
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... AD9271 Pin No. Name 18 LOSW-H 19 LI-H 20 LG-H 23 CLK− 24 CLK+ 27 DOUTH− 28 DOUTH+ 29 DOUTG− 30 DOUTG+ 31 DOUTF− 32 DOUTF+ 33 DOUTE− 34 DOUTE+ 35 DCO− 36 DCO+ 37 FCO− 38 FCO+ 39 DOUTD− 40 DOUTD+ 41 DOUTC− 42 DOUTC+ 43 DOUTB− 44 DOUTB+ 45 DOUTA− 46 DOUTA+ 48 STBY 49 PDWN 51 SCLK ...
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... CW Doppler Output True for Channel 3 CW Doppler Output Complement for Channel 4 CW Doppler Output True for Channel 4 CW Doppler Output Complement for Channel 5 CW Doppler Output True for Channel 5 LNA Analog Output for Channel E LNA Analog Output Complement for Channel E Rev Page AD9271 ...
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... AD9271 EQUIVALENT CIRCUITS AVDD VCM 15kΩ LI-x, LG-x Figure 5. Equivalent LNA Input Circuit 10Ω LO-x, LOSW-x Figure 6. Equivalent LNA Output Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit AVDD 1.25V SCLK OR PDWN Rev Page AVDD 350Ω ...
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... Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit GAIN+ Figure 15. Equivalent GAIN+ Input Circuit GAIN– Figure 16. Equivalent GAIN− Input Circuit CWDx+, CWDx– Figure 17. Equivalent CWDx± Output Circuit Rev Page AD9271 AVDD 6kΩ 50Ω 40kΩ +0.5V 10Ω ...
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... AD9271 TYPICAL PERFORMANCE CHARACTERISTICS MSPS MHz, LPF = 1/3 × f SAMPLE IN 2.0 1.5 1.0 0.5 +85°C 0 +25°C –40°C –0.5 –1.0 –1.5 –2.0 0 0.1 0.2 0.3 0.4 0.5 0.6 V (V) GAIN Figure 18. Gain Error vs Three Temperatures GAIN 20 SAMPLE SIZE = 720 CHANNELS –1.0 –0.8 – ...
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... Figure 27. Short-Circuit, Output-Referred Noise vs 0.0 V GAIN 64.0 63.5 63.0 62.5 62.0 61.5 61.0 60.5 60.0 59 1.0 V Figure 28. SNR/SINAD vs. V GAIN 1.70 1.65 1.60 1.55 1.50 1.45 1. –40 Figure 29. Short-Circuit, Input-Referred Noise vs. Temperature Rev Page AD9271 LNA GAIN = 8× LNA GAIN = 6× LNA GAIN = 5× 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 V (V) GAIN GAIN SNR (dBFS) SINAD (dBFS) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 V (V) GAIN , AIN = −6.5 dBFS GAIN – ...
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... AD9271 0 –5 –3dB LINE –10 –15 (1/3) × 40MSPS –20 –25 –30 (1/3) × 25MSPS –35 –40 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY (MHz) Figure 30. Antialiasing Filter (AAF) Pass-Band Response, No HPF Applied 300 V = 0.5V GAIN 250 V = 1.0V GAIN 200 150 100 0.1 1 ANALOG INPUT FREQUENCY (MHz) Figure 31. Antialiasing Filter (AAF) Group Delay Response – ...
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... INPUT AMPLITUDE (dBFS) Figure 37. IMD3 vs. Amplitude 0 –20 –40 –60 –80 –100 –120 0 0.9 1.0 Figure 38. Typical IMD3 and IMD2 Performance –15 –10 –5 Rev Page AD9271 AIN1 = AIN2 = –7dBFS f1 = 5MHz f2 = 6MHz IMD2 = –70.59dBc IMD3 = –64.45dBc GAIN FREQUENCY (MHz) ...
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... AD9271 THEORY OF OPERATION ULTRASOUND The primary application for the AD9271 is medical ultrasound. Figure 39 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution ...
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... LI-x. This technique is well known and results in the input LOSW-x VCM resistance shown in Equation 1: LO-x LG-x CLG where A/2 is the single-ended gain or the gain from the LI-x inputs to the LO-x outputs. Rev Page 12-BIT SERIAL +24dB PIPELINE LVDS ADC AAF AD9271 AD9271 CDWx+ CDWx– DOUTx– DOUTx+ (1) ...
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... AD9271 Because the amplifier has a gain of 6× from its input to its differential output important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and less than the gain of the amplifier, or 9.6 dB (3×). The input resistance is reduced by an internal bias resistor of 15 kΩ in parallel with the source resistance connected to Pin LI-x, with Pin LG-x ac grounded ...
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... With the diodes shown in Figure 46, clamping levels of ±0 less significantly enhance the overload performance of the system. to preserve the S for various values S Rev Page +5V Tx 5kΩ DRIVER HV 10nF BAS40-04 2kΩ 10nF 5kΩ TRANSDUCER –5V Figure 46. Input Overload Protection AD9271 AD9271 LNA ...
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... LNA g m Figure 47. Typical CW Doppler System Using the AD9271 and AD8333 or AD8339 gain, and it defines a focal point within the body from which the location of the returning echo is derived. The AD9271 includes the front-end components needed to implement analog beam forming for CW Doppler operation. ...
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... I/V conversion to ensure that the full-scale swing and common-mode voltage are within the operating limits of the AD9271. When interfacing to the AD8339, a common- mode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are desired. This can be accomplished by connecting an inductor between each CWD output and a 2 ...
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... Figure 52. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accom- modate full-scale input. AD9271 – POSTAMP AD9271 GAIN+ GAIN– VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The ...
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... ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. ADC The AD9271 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages ...
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... This allows a wide range of clock input duty cycles without affecting the performance of the AD9271. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode ...
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... The AD9271 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. 16 BITS By asserting the STBY pin high, the AD9271 is placed into a 14 BITS standby mode. In this state, the device typically dissipates 12 BITS 65 mW ...
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... AD9271 Digital Outputs and Timing The AD9271 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard by using the SDIO pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW ...
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... Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4 Rev Page 600 EYE: ALL BITS ULS: 2396/2396 400 200 0 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns –200ps –100ps 0ps 100ps AD9271 1.0ns 1.5ns 200p s ...
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... Two output clocks are provided to assist in capturing data from the AD9271. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9271 and must be captured on the rising and falling edges of the DCO± ...
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... A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s and the AD9271 inverts the bit stream with relation to the ITU standard (see Table 11 for the initial values). Table 11. PN Sequence ...
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... AD9271 Internal Reference Operation A comparator within the AD9271 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 66), setting VREF The REFT and REFB pins establish their input span of the ADC core from the reference configuration ...
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... The pins described in Table 13 constitute the physical interface between the user’s programming device and the serial port of the AD9271. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. ...
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... AD9271 This interface is flexible enough to be controlled by either serial PROMs or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the device (see the AN-812 Application Note CSB SCLK DON’T CARE R SDIO DON’ ...
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... LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit. ” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Rev Page AD9271 ...
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... X X Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset off 0 = off (default) (default) Chip ID Bits [7:0] (AD9271 = 0x13), (default) Child ID [5: (identify device variants of Chip ID MSPS (default MSPS MSPS X X Data Data Channel Channel ...
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... Rev Page AD9271 Bit 0 Default Notes/ Bit 1 (LSB) Value ...
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... AD9271 Addr. Bit 7 (Hex) Register Name (MSB) Bit 6 19 user_patt1_lsb user_patt1_msb B15 B14 1B user_patt2_lsb user_patt2_msb B15 B14 21 serial_control LSB first off (default) 22 serial_ch_stat flex_filter X Enable automatic low-pass tuning off (default) 2C analog_input cross_point_switch undefined feature ...
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... APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9271 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power and Ground Recommendations When connecting power to the AD9271 recommended that two separate 1 ...
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... The LNA is driven differentially through a transformer. Figure 73 shows the typical bench characterization setup used to evaluate the ac performance of the AD9271 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain ...
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... P3A and P4A on the AD8339 evaluation board, and snap the standoffs labeled MH502, MH504, and MH505 that are provided with the AD9271 into the AD8339 evaluation board standoff holes in the center of the board. The standoffs automatically lock into place and create a direct connection between the AD9271 CWDx± ...
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... AD9271 QUICK START PROCEDURE The following is a list of the default and optional settings when using the AD9271 either on the evaluation board or at the system level design evaluation board is not being used, follow only the SPI controller steps. When using the AD9271 evaluation board, 1 ...
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... SCHEMATICS AND ARTWORK Figure 75. Evaluation Board Schematic, DUT Analog Input Circuits Rev Page AD9271 06304-086 ...
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... AD9271 Figure 76. Evaluation Board Schematic, DUT Analog Input Circuits (Continued) Rev Page 06304-087 ...
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... Figure 77. Evaluation Board Schematic, DUT, VREF, and Gain Circuitry Vref Selec t R31 1 Vref = External R31 5 0-DN P 0-DN P R31 2 DNP R31 6 Vref=0.5V(1+R313/R312) 0-DN P R31 3 DNP Vref=1V R31 7 0 Remove C307 when using external Vref Rev Page AD9271 06304-088 AVD D D AVD 50 N PDW 49 STDBY 48 DRVDD_DUT DRVDD 47 CHA + DOUTA 46 DOUTA - ...
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... AD9271 GND RSET 32 1 AVDD_3. Figure 78. Evaluation Board Schematic, Clock and CW Doppler Circuitry Rev Page 06304-089 0.1UF 0.1UF 11 C410 C409 ...
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... SDO_CHA 8 SDI_CHA SCLK_CH A 4 CSB1_CHA 1 2 J501 Figure 79. Evaluation Board Schematic, Power Supply and SPI Interface Circuitry E704 E708 1 1 E703 E707 1 1 E702 E706 1 1 E701 E705 1 1 GND 1 Rev Page AD9271 06304-090 GND 1 GND 1 ...
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... AD9271 FIFO5: DATA BUS 1 CONNECTOR 6469169-1 P60 1 GNDCD1 GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDAB1 0 30 DCO ...
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... Figure 81. Evaluation Board Layout, Top Side Figure 82. Evaluation Board Layout, Ground Plane (Layer 2) Rev Page AD9271 ...
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... AD9271 Figure 83. Evaluation Board Layout, Power Plane (Layer 3) Figure 84. Evaluation Board Layout, Power Plane (Layer 4) Rev Page ...
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... Figure 85. Evaluation Board Layout, Ground Plane (Layer 5) Figure 86. Evaluation Board Layout, Bottom Side Rev Page AD9271 ...
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... AD9271 Table 16. Evaluation Board Bill of Materials (BOM) Item Qty. Reference Designator 1 70 C101, C103, C105, C107, C109, C111, C113, C115, C121, C122, C123, C124, C201, C203, C205, C207, C209, C211, C213, C215, C221, C222, C223, C224, C301, C303, C304, C305, C306, C308, C309, C401, ...
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... Resistor 402 0 Ω, 1/ tol Resistor 402 200 Ω, 1/ tol Resistor 402 49.9 Ω, 1/16 W, 0.5% tol Resistor 402 10 kΩ, 1/ tol Rev Page AD9271 Manufacturer RoHS Part Number 2 Samtec TSW-104-08-T-D 2 Samtec TSW-102-07-G-S 2 Samtec SSW-104-06-G-D 2 Wieland Z5.531.3325.0 2 Samtec TSW-103-07-G-S 2 ...
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... Murata PVA2A103A01R00 2 Panasonic ERJ-2RKF4121X NIC NRC04F4121TRF 2 Components 2 Yageo RC0402JR-07240RL NIC NRC04J241TRF 2 Components 2 NIC NRC04F8061TRF Components 2 NIC NRC04F1270TRF Components NRC04J751TRF 2 NIC Components Valpey Fisher VFAC3-BHL-50MHz CTS CB3LV-3C-50M0000-T Mini-Circuits® ADT1-1WT+ Mini-Circuits ADTT4-1+ Analog AD9271BSVZ-50 Devices Analog ADR510ARTZ Devices Analog AD9515BCPZ Devices ...
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... IC SOT223-2 Regulator IC SOT223-2 Regulator IC SC88 NC7WZ07, dual buffer, SC88 IC SC88 NC7WZ16P6X, UHS dual buffer, SC88 Rev Page AD9271 Manufacturer RoHS Part Number Analog AD812ARZ Devices Analog ADP3335ACPZ-2.5 Devices Analog ADP3339AKCZ-1.8 Devices Analog ADP3339AKCZ-3.3 Devices 2 Fairchild NC7WZ07P6X_NL ...
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... Model Range 1 AD9271BSVZ-50 −40°C to +85°C 1 AD9271BSVZRL-50 −40°C to +85°C 1 AD9271BSVZ-40 −40°C to +85°C 1 AD9271BSVZRL-40 −40°C to +85°C 1 AD9271BSVZ-25 −40°C to +85°C 1 AD9271BSVZRL-25 −40°C to +85° RoHS Compliant Part. 16.00 BSC SQ 1.20 MAX 14.00 BSC SQ 100 ...
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... NOTES Rev Page AD9271 ...
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... AD9271 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06304-0-5/09(B) Rev Page ...