LTC1417ACGN Linear Technology, LTC1417ACGN Datasheet - Page 22

• Manufacturer Part Number: LTC1417ACGN
• Description: IC A/D CONV 14BIT SAMPLNG 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC1417ACGN

• Number Of Bits: 14
• Sampling Rate (per Second): 400k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 27.5mW Unipolar; 44mW Bipolar
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EXTCLKIN
APPLICATIONS
LTC1417
Using an External Conversion Clock and an External
Data Clock. In Figure 20, data is also output after each
conversion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 19 except that
an external clock is used for the conversion. This mode
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
22
CONVST
BUSY
D
SCLK
OUT
RD
t
t
dEXTCLKIN
3
t
2
1
U
2
(SAMPLE N)
3
Figure 20. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY Indicates End of Conversion
4
INFORMATION
U
5
HOLD
6
t
CONV
7
CONVST
Hi-Z
8
W
9 10 11 12 13 14 15 16
13
CONVST
U
LTC1417
EXTCLKIN
BUSY
SCLK
D
OUT
RD
t
4
14
9
6
12
7
D13
t
Figure 19, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conver-
sion clock must be between 30kHz and 9MHz to maintain
accuracy. If more than 16 SCLKs are provided, more zeros
will be filled in after the data word indefinitely. To select the
external conversion clock, apply an external conversion
clock to EXTCLKIN. The external SCLK is applied to SCLK.
RD can be used to gate the external SCLK such that data will
be clocked out only after RD goes low.
6
1
t
10
t
7
12 11 10 9
2
3
4
SCLK
D
5
OUT
DATA N
8
6
CLKOUT
INT
C0
SCK
MISO
P OR DSP
7
7
t
t
6
V
8
5
9
SAMPLE
D13
IL
5
9 10 11 12 13 14 15 16
t
12
4
t
t
11
LSCLK
3
RISING CLOCK
CAPTURE ON
2
1
0
D12
t
HSCLK
ZEROS
FILL
FALLING CLOCK
CAPTURE ON
t
8
Hi-Z
sn1417 1417fas
D11
1
1417 F20
2
V
V
OH
OL
3 4