SI5326C-B-GM Silicon Laboratories Inc, SI5326C-B-GM Datasheet - Page 28

IC ANY-RATE MULTI/ATTEN 36QFN

SI5326C-B-GM

Manufacturer Part Number
SI5326C-B-GM
Description
IC ANY-RATE MULTI/ATTEN 36QFN
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Datasheets

Specifications of SI5326C-B-GM

Number Of Circuits
1
Package / Case
36-QFN
Pll
Yes
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Ratio - Input:output
2:2
Differential - Input:output
Yes/Yes
Frequency - Max
346MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
1.62 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
346MHz
Maximum Input Frequency
710 MHz
Minimum Input Frequency
0.002 MHz
Output Frequency Range
0.002 MHz to 1400 MHz
Supply Voltage (max)
3.63 V
Supply Voltage (min)
1.71 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Si5326
Reset value = 0000 0000
Reset value = 1100 0000
28
Register 8.
Register 9.
Name
Name
Type
Type
7:6
5:4
3:0
7:3
2:0
Bit
Bit
Bit
Bit
HLOG_2 [1:0] HLOG_2 [1:0].
HIST_AVG
Reserved
Reserved
Name
Name
D7
D7
[4:0]
HLOG_2[1:0]
R/W
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
Reserved.
HIST_AVG [4:0].
Selects amount of averaging time to be used in generating the history information for
Digital Hold.
See the Si53xx Family Reference Manual for a detailed description
Reserved.
D6
D6
HIST_AVG [4:0]
R/W
D5
D5
HLOG_1[1:0]
R/W
Rev. 1.0
D4
D4
Function
Function
D3
D3
D2
D2
R
Reserved
R
Reserved
D1
D1
R
D0
D0
R

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