SI5326C-B-GM Silicon Laboratories Inc, SI5326C-B-GM Datasheet - Page 24

IC ANY-RATE MULTI/ATTEN 36QFN

SI5326C-B-GM

Manufacturer Part Number
SI5326C-B-GM
Description
IC ANY-RATE MULTI/ATTEN 36QFN
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Datasheets

Specifications of SI5326C-B-GM

Number Of Circuits
1
Package / Case
36-QFN
Pll
Yes
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Ratio - Input:output
2:2
Differential - Input:output
Yes/Yes
Frequency - Max
346MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
1.62 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Frequency-max
346MHz
Maximum Input Frequency
710 MHz
Minimum Input Frequency
0.002 MHz
Output Frequency Range
0.002 MHz to 1400 MHz
Supply Voltage (max)
3.63 V
Supply Voltage (min)
1.71 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Si5326
Reset value = 0000 0101
24
Register 3.
Name
Type
7:6
3:0
Bit
Bit
5
4
CKSEL_REG
SQ_ICAL
Reserved
DHOLD
CKSEL_REG [1:0]
Name
D7
[1:0]
R/W
CKSEL_REG.
If the device is operating in register-based manual clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock
will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the CS_CA
input pin continues to control clock selection and
00: CKIN_1 selected.
01: CKIN_2 selected.
10: Reserved
11: Reserved
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the
input clocks.
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 8 on page 19.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
Reserved.
D6
DHOLD
R/W
D5
SQ_ICAL
R/W
Rev. 1.0
D4
Function
D3
CKSEL_REG is of no consequence
D2
Reserved
R
D1
.
D0

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