SI5326C-B-GM Silicon Laboratories Inc, SI5326C-B-GM Datasheet - Page 17

• Manufacturer Part Number: SI5326C-B-GM
• Description: IC ANY-RATE MULTI/ATTEN 36QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5326C-B-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 346MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.62 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 346MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1400 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Typical Application Circuit
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide.
Option 1:
Option 2:
Input
Clock
Sources*
Option 1:
Option 2:
Figure 5. Si5326 Typical Application Circuit (SPI Control Mode)
Figure 4. Si5326 Typical Application Circuit (I
Control Mode (L)
Crystal/Ref Clk Rate
Input
Clock
Sources*
Control Mode (H)
Crystal/Ref Clk Rate
Crystal
Reset
Refclk+
Refclk–
Crystal
130 
130 
82 
82 
Reset
Refclk+
Refclk–
130 
130 
82 
82 
V
V
DD
DD
= 3.3 V
= 3.3 V
V
V
DD
DD
= 3.3 V
= 3.3 V
V
DD
15 k
15 k
130 
130 
82 
82 
V
0.1 µF
0.1 µF
Notes:
DD
15 k
15 k
130 
130 
82 
82 
0.1 µF
0.1 µF
Notes:
System
Supply
Power
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. I
CKIN2+
CKIN2–
CMODE
RST
CKIN1+
CKIN1–
XA
XB
RATE[1:0]
XA
XB
System
Supply
Power
2
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
C-required pull-up resistors not shown.
CKIN2+
CKIN2–
CMODE
RST
CKIN1+
CKIN1–
XA
XB
RATE[1:0]
XA
XB
2
Ferrite
Bead
2
Ferrite
Bead
Si5326
Si5326
Rev. 1.0
C
C
C
C
4
1
2
3
C
C
C
C
1 µF
0.1 µF
0.1 µF
0.1 µF
1
2
3
4
1 µF
0.1 µF
0.1 µF
0.1 µF
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
INT_C1B
CS_CA
CKOUT1+
CKOUT1–
CKOUT2+
CKOUT2–
A[2:0]
SDA
INT_C1B
DEC
SCL
C2B
LOL
CS_CA
INC
SCLK
SDO
DEC
C2B
LOL
SDI
INC
SS
0.1 µF
0.1 µF
0.1 µF
0.1 µF
2
0.1 µF
0.1 µF
0.1 µF
0.1 µF
100 
100 
Output Phase Control
C Control Mode)
Output Phase Control
100 
100 
Interrupt/CKIN1 Invalid Indicator
CKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Serial Port Address
Serial Data
Serial Clock
Clock Select/Clock Active
Interrupt/CLKIN1 Invalid Indicator
CLKIN2 Invalid Indicator
PLL Loss of Lock Indicator
Slave Select
Serial Data Out
Serial Data In
Serial Clock
Clock Select/Clock Active
+
–
+
–
+
+
–
–
I2C Interface
Clock Outputs
SPI Interface
Clock Outputs
Si5326
17