SI5326C-B-GM Silicon Laboratories Inc, SI5326C-B-GM Datasheet - Page 22

• Manufacturer Part Number: SI5326C-B-GM
• Description: IC ANY-RATE MULTI/ATTEN 36QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5326C-B-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 346MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.62 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 346MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 0.002 MHz
• Output Frequency Range: 0.002 MHz to 1400 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5326
6. Register Descriptions
Reset value = 0001 0100
22
Register 0.
Name
Type
4:2
Bit
Bit
7
6
5
1
0
ALWAYS_ON
FREE_RUN
BYPASS_
Reserved
Reserved
Reserved
CKOUT_
Name
D7
REG
R
FREE_
Reserved.
Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB
reference.
0: Disable
1: Enable
CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on
and ICAL is not complete or successful. See Table 8 on page 19.
0: Squelch output until part is calibrated (ICAL).
1: Provide an output. Note: The frequency may be significantly off and variable until the
part is calibrated.
Reserved.
Bypass Register.
This bit enables or disables the PLL bypass mode. Use only when the device is in digital
hold or before the first ICAL.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing the
PLL. Bypass mode does not support CMOS clock outputs.
Reserved.
RUN
R/W
D6
ALWAYS_
CKOUT_
R/W
ON
D5
Rev. 1.0
D4
R
Function
D3
R
D2
R
BYPASS_
REG
R/W
D1
D0
R